HV746
Dual High Speed ±75V 2.5A Ultrasound Pulser
Features
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HVCMOS technology for high performance
High density integration ultrasound transmitter
0 to ±75V output voltage
±2.5A source and sink current in PW mode
±800mA source and sink current in CW mode
Up to 20MHz operation frequency
Matched delay times
1.2V to 5.0V CMOS logic interface
Over temperature sensing
Under voltage protections
Built-in output drain bleed resistors
General Description
The Supertex HV746 is a dual-channel monolithic high voltage
high-speed pulse generator. It is designed for portable medical
ultrasound applications. This high voltage and high-speed
integrated circuit can also be used for other piezoelectric,
capacitive or MEMS sensor in ultrasonic nondestructive
detection and sonar ranger applications.
The HV746 consists of controller logic interface circuit, level
translators, MOSFET gate drives and high current power P-
channel and N-channel MOSFETs as the output stage for
each channel. A 2-bit mode control is provided that allows the
maximum output current to be reduced for power saving.
The output stages of each channel are designed to provide
peak output currents over ±3.6A for pulsing, when in mode
4, with up to ±75V swings. When in mode 1, all the output
stages drop the peak current to ±800mA for low-voltage CW
mode operation to save power consumption of the IC. The P
and N type of power FETs gate drivers are supplied by two
floating 9.0VDC power supplies reference to V
PP
and V
NN
. This
direct coupling topology of the gate drivers not only saves two
high voltage capacitors per channel, but also makes the PCB
layout easier.
Applications
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Portable medical ultrasound imaging
Piezoelectric transducer drivers
NDT ultrasound equipment
Pulse waveform generator
Typical Application Circuit
+1.8 to 3.3V
C1
VLL
OT P
EN
MC0
MC1
PIN1
+1.8 to 3.3V
Logic
EN_P WR
+9V
C2
VDD
SU B
RGND
RP1
C3
VSUB
+75V
VPP -9V
C4
VPF
VPP
0 to +75V
C5
Level
Translator
P-Driver
TXP1
D1
HVOUT1
NIN1
Level
Translator
TXN1
D2
N-Driver
RN1
X1
1 of 2 Channels
RGND
VNN
C7
C6
VNN +9V
0 to -75V
GREF
VSS
HV746
VNF
HV746
Ordering Information
Package Options
Device
HV746
48-Lead QFN
7x7mm body, 1.0mm height (max), 0.5mm pitch
HV746K6-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
V
SS
, Power supply reference
V
LL
, Positive logic supply
V
DD
, Positive logic and level translator supply
(V
PP
-V
PF
) Positive floating gate drive supply
(V
NF
- V
NN
) Negative gate floating drive supply
(V
PP
-V
NN
) Differential high voltage supply
V
PP
, High voltage positive supply
V
NN
, High voltage negative supply
All logic input PIN, NIN and EN pin voltages
OTP, over temperature protection output
(V
SUB
- V
SS
) Substrate to V
SS
voltage difference
(V
PP
–TXP
X
) V
PP
to TXP
X
voltage difference
(V
SUB
- TXP
X
) Substrate to TXP
X
voltage difference
(TXN
X
-V
NN
) TXN
X
to V
NN
voltage difference
dV
PP
/dt, HV positive supply maximum slew rate
dV
NN
/dt, HV negative supply maximum slew rate
Storage temperature
Thermal resistance, θ
JA
(4-layer,1oz, 4x3in. 9-via PCB)
Thermal resistance, θ
JC
Value
0V
-0.5V to +7V
-0.5V to +14V
-0.5V to +14V
-0.5V to +14V
+180V
-0.5V to +95V
+0.5V to -95V
-0.5V to +7.0V
-0.5V to +7.0V
+180V
+180V
+180V
+180V
25V/μs
25V/μs
-65°C to 150°C
29°C/W
0.5°C/W
Pin Configuration
48
1
48-Lead QFN (K6)
(Top View)
Package Marking
HV746K6
LLLLLLLLL
YYWW
AAA CCC
L = Lot Number
YY = Year Sealed
WW = Week Sealed
A = Assembler ID
C = Country of Origin
= “Green” Packaging
48-Lead QFN (K6)
Absolute Maximum Ratings are those values beyond which damage to the device may
occur. Functional operation under these conditions is not implied. Continuous operation
of the device at the absolute rating level may affect device reliability. All voltages are
referenced to device ground.
Power-Up Sequence
1
2
3
4
5
6
V
SUB
V
LL
with logic signal low
V
DD
(V
PP
–V
PF
) and (V
NF
–V
NN
)
V
PP
and V
NN
Logic control signals go to hi
Power-Down Sequence
1
2
3
4
5
6
Logic control signals go to low
V
PP
and V
NN
(V
PP
–V
PF
) and (V
NF
–V
NN
)
V
DD
V
LL
V
SUB
2
HV746
Operating Supply Voltages and Current (2 Channel Active)
(Operating conditions, unless otherwise specified, V
SS
= 0V, V
LL
= +3.3V, V
DD
= +9.0V, V
PP
-V
PF
= +9.0V, V
NN
- V
NF
= -9.0V, V
PP
= +75V, V
NN
= -75V,T
A
= 25°C)
Sym
V
LL
V
DD
V
PF
V
NF
V
SUB
V
PP
V
NN
SR
MAX
I
LL
I
DDQ
I
DDEN
I
DDEN
I
DDENCW
I
PPQ
I
PPEN
I
PPENCW
I
NNQ
I
NNEN
I
NNENCW
I
PFQ
I
PFEN
I
PFENCW
I
NFQ
I
NFEN
I
NFENCW
Parameter
Logic voltage reference
Internal voltage supply
P-FET gate driver supply
N-FET gate drive supply
IC substrate voltage
Positive HV supply
Negative HV supply
Slew rate limit of V
PP
, V
NN
V
LL
Current EN = Low
V
DD
Current EN = Low
V
DD
Current EN = High
V
DD
Current MODE = 4
V
DD
Current MODE = 1
V
PP
Current EN = Low
V
PP
Current MODE = 4
V
PP
Current MODE = 1
V
NN
Current EN = Low
V
NN
Current MODE = 4
V
NN
Current MODE = 1
V
PF
Current EN = Low
V
PF
Current MODE = 4
V
PF
Current MODE = 1
V
NF
Current EN = Low
V
NF
Current MODE = 4
V
NF
Current MODE = 1
Min
1.2
8.0
(V
PP
-12)
Typ
1.8 to 3.3
9.0
(V
PP
-9.0)
Max
5.0
12
(V
PP
-8.0)
Units Conditions
V
V
V
V
V
V
V
V/ms
μA
μA
mA
mA
μA
mA
μA
mA
μA
mA
μA
mA
---
---
Floating driver voltage
supplies.
Must connect to the most
positive potential of the IC.
---
---
Built-in slew rate detection
protection.
---
---
f = 0MHz
f = 5.0MHz, continuous,
no loads
---
f = 5.0MHz, continuous,
no loads
---
f = 5.0MHz, continuous,
no loads
---
f = 5.0MHz, continuous,
no loads
---
f = 5.0MHz, continuous,
no loads
(V
NN
+8.0) (V
NN
+9.0) (V
NN
+12)
V
DD
0
-75
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
V
PP
-
-
-
35
15
0.75
0.75
2.0
10
250
170
15
250
170
10
50
12
20
25
12
+75
+75
0
25
120
-
2.0
-
-
25
-
-
30
-
-
25
-
-
30
-
-
Under Voltage and Over Temperature Protection
Sym
V
PULL_UP
V
UVDD
V
UVLL
V
UVVF
V
OL_OTP
I
OTP
T
OTP
T
HYS
Parameter
Open drain pull-up voltage
V
DD
threshold
V
LL
threshold
V
PF
, V
NF
threshold
OTP flag output low voltage
Max. open drain output current
Over temperature threshold
OTP output reset hysteresis
Min
-
4.5
0.8
4.5
-
-
95
-
Typ
-
-
0.9
-
-
1.0
110
7.0
Max
5.0
6.0
1.0
6.0
1.0
-
125
-
Units Conditions
V
V
V
V
V
mA
°C
°C
---
---
---
---
V
LL
= 3.3V, OTP = Active,
I
PULL-UP
= 1.0mA
V
LL
= 3.3V, OTP = Active,
I
PULL-UP
= 1.0mA
If over temperature occurs, OTP
low and all TX outputs will be
HiZ.
3
HV746
DC Electrical Characteristics
Sym
I
OUT
R
ON
C
OSS
Parameter
Output saturation current
Channel resistance
Output capacitance
(Operating conditions, unless otherwise specified, V
SS
= 0V, V
LL
= +3.3V, V
DD
= +9.0V, V
PP
-V
PF
= +9.0V, V
NN
- V
NF
= -9.0V, V
PP
= +75V, V
NN
= -75V,T
A
= 25°C)
Output P-Channel MOSFET, TXP (Mode 4)
Min
2.5
-
-
Typ
3.6
4.0
200
Max
-
-
-
Units Conditions
A
Ω
pF
---
I
SD
= 100mA
V
DS
= 25V, f = 1.0MHz
Output N-Channel MOSFET, TXN (Mode 4)
Sym
I
OUT
R
ON
C
OSS
Parameter
Output saturation current
Channel resistance
Output capacitance
Min
2.5
-
-
Typ
3.6
3.75
80
Max
-
-
-
Units Conditions
A
Ω
pF
---
I
SD
= 100mA
V
DS
= 25V, f = 1.0MHz
MOSFET Drain Bleed Resistor
Sym
R
P/N1~4
P
RO
Parameter
Output bleed resistance
Bleed resistors power limit
Min
5.0
-
Typ
7.5
-
Max
10
80
Units Conditions
kΩ
mW
---
---
Logic Inputs
Sym
V
IH
V
IL
I
IH
I
IL
C
IN
Parameter
Input logic high voltage
Input logic low voltage
Input logic high current
Input logic low current
Input logic capacitance
Min
(V
LL
- 0.4)
0
-
-10
-
Typ
-
-
-
-
-
Max
V
LL
0.4
10
-
10
Units Conditions
V
V
μA
μA
pF
---
---
---
---
---
AC Electrical Characteristics
(Operating conditions, unless otherwise specified, V
SS
= 0V, V
LL
= +3.3V, V
DD
= +9.0V, V
PP
-V
PF
= +9.0V, V
NN
- V
NF
= -9.0V, V
PP
= +75V, V
NN
= -75V,T
A
= 25°C)
Sym
t
r
t
f
f
OUT
HD2
t
EN
t
DIS
t
dr
t
df
t
dm
Δt
delay
t
J
Parameter
Output rise time
Output fall time
Output frequency range
Second harmonic distortion
Enable time
Disable time
Delay time on inputs rise
Delay time on inputs fall
Delay on mode change
|t
dr
- t
df
| delay time matching
Delay jitter on rise or fall
Min
-
-
-
-
-
-
-
-
-
-
-
Typ
18
18
-
-28
180
2.8
22
22
2.5
±2.0
15
Max
-
-
20
-
500
10
-
-
10
-
-
Units Conditions
ns
ns
MHz
dB
μs
μs
ns
ns
ns
ns
ns
V
PP
/V
NN
= +/-25V, input t
r
50% to
HV
OUT
t
r
or t
f
50%,
with 330pF//2.5kΩ load
100Ω resistor load
330pF//2.5kΩ load
4
HV746
Switching Time Diagram
NINx
50%
PINx
t
dr
90%
50%
t
df
V
PP
Output
10%
t
r
t
f
0
10%
V
NN
90%
Drive Mode Control Table
Mode
1
2
3
4
MC1
0
0
1
1
MC0
0
1
0
1
I
SC
(A)
R
ON P
(Ω)
R
ON N
(Ω)
0.82
1.16
1.94
3.6
18
13
7.5
4.0
17
12
7.0
3.8
Note:
1. V
PP
/V
NN
= +/-75V, V
DD
= (V
PP
–V
PF
) = (V
NF
–V
NN
) = +9.0V
2. I
SC
is current into 1.0Ω to GND
3. Ron calculated from V
OUT
into 100Ω load
Truth Table (Mode = X)
Logic Inputs
EN
1
1
1
1
0
Note:
* Not allowed, may damage IC.
Output
NIN
X
0
0
1
1
X
TXP
X
OFF
ON
OFF
ON*
OFF
TXN
X
OFF
OFF
ON
ON*
OFF
PIN
X
0
1
0
1
X
5
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