MD1210
High Speed Dual MOSFET Driver
Features
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6ns rise and fall time with 1000pF load
2.0A peak output source/sink current
1.2V to 5V input CMOS compatible
4.5V to 13V total supply voltage
Smart Logic threshold
Low jitter design
Two matched channels
Outputs can swing below ground
Low inductance package
Thermally-enhanced package
General Description
The Supertex MD1210 is a high speed, dual MOSFET driver.
It is designed to drive high voltage P and N-channel MOSFET
transistors for medical ultrasound and other applications requiring
a high output current for a capacitive load. The high-speed input
stage of the MD1210 can operate from 1.2V to 5.0V logic interface
with an optimum operating input signal range of 1.8V to 3.3V. An
adaptive threshold circuit is used to set the level translator switch
threshold to the average of the input logic 0 and logic 1 levels.
The input logic levels may be ground referenced, even though
the driver is putting out bipolar signals. The level translator uses
a proprietary circuit, which provides DC coupling together with
high-speed operation.
V
DD1
, V
DD2
, and V
H
should be connected to the positive supply
voltage, and V
SS1
, V
SS2
, and V
L
should be connected to 0V or to
Ground. The GND pin is the logic control input signal digital ground.
The output stage is capable of peak currents of up to ±2.0A,
depending on the supply voltages used and load capacitance
present.
The OE pin serves a dual purpose. First, its logic H level is used
to compute the threshold voltage level for the channel input level
translators. Secondly, when OE is low, the outputs are disabled,
with the A output high and the B output low. This assists in properly
pre-charging the AC coupling capacitors that may be used in
series in the gate drive circuit of an external PMOS and NMOS
transistor pair.
Applications
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Medical ultrasound imaging
Piezoelectric transducer drivers
Nondestructive evaluation
PIN diode driver
CCD Clock driver/buffer
High speed level translator
Typical Application Circuit
+12V
V
DD
1
OE
Level
Shifter
Level
Shifter
OUT
A
+100V
1µF
V
DD
2
V
H
0.47µF
IN
A
10nF
3.3V CMOS
Logic Inputs
V
SS
2
V
L
V
H
V
DD
2
10nF
IN
B
Level
Shifter
-100V
To Piezoelectric
Transducer
OUT
B
Supertex
TC6320TG
1µF
MD1210
Gnd
V
SS
1
V
SS
2
V
L
MD1210
Ordering Information
DEVICE
MD1210
Package Option
12-Lead 4x4x0.8pitch QFN
MD1210K6-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Parameter
V
DD1
,V
DD2
, V
H
- supply voltage
V
SS1
,V
SS2
, V
L
- supply voltage
Logic input levels
Maximum junction temperature
Storage temperature
Operating temperature
Value
-0.5V to +13.5V
0V
-0.5V to 7.0V
+125°C
-65°C to 150°C
-20°C to 85°C
Pin Configuration
12
10
1
9
3
7
Absolute Maximum Ratings are those values beyond which damage to
the device may occur. Functional operation under these conditions is
not implied. Continuous operation of the device at the absolute rating
level may affect device reliability. All voltages are referenced to device
ground.
4
QFN
(top view)
6
DC Electrical Characteristics
(Over operating conditions unless otherwise specified, V
H
= V
DD1
= V
DD2
= 12V, V
L
= V
SS1
= V
SS2
= 0V, V
OE
= 3.3V, T
J
= 25°C)
Sym
V
DD1
,
V
DD2
V
H
V
L
I
DD1Q
I
DD2Q
I
HQ
I
DD1
I
DD2
I
H
V
IH
V
IL
I
IH
I
IL
V
IH
V
IL
R
IN
C
IN
θ
JA
θ
JC
Parameter
Supply voltage
Output high supply voltage
Output low supply voltage
V
DD1
quiescent current
V
DD2
quiescent current
V
H
quiescent current
V
DD1
average current
V
DD2
average current
V
H
average current
Input logic voltage high
Input logic voltage low
Input logic current high
Input logic current low
OE Input logic voltage high
OE Input logic voltage low
Input logic impedance to GND
Logic input capacitance
Thermal resistance to air
Thermal resistance to case
Min
4.5
V
SS
+ 2.0
-
-
-
-
-
-
-
V
OE
- 0.3
0
-
-
1.2
0
12
-
-
-
Typ
-
-
-
0.55
-
-
0.88
6.6
23
-
-
-
-
-
-
20
5.0
47
7.0
2
Max
13
V
DD
V
DD
- 2.0
-
10
10
-
-
-
5.0
0.3
1.0
1.0
5.0
0.3
30
10
-
-
Units Conditions
V
V
V
mA
µA
µA
mA
mA
mA
V
V
µA
µA
V
V
KΩ
pF
°C/W
°C/W
All inputs
1oz. 4-layer 3x4” PCB with thermal
pad and thermal via array
---
For logic input OE
For logic inputs INA and INB
One channel on at 5.0Mhz,
No load
No input transitions
---
---
---
MD1210
Application Information
For proper operation of the MD1210, low inductance bypass
capacitors should be used on the various supply pins. The
GND input pin should be connected to the digital ground.
The IN
A
, IN
B
, and OE pins should be connected to their logic
source with a swing of GND to logic level high, which is 1.2V
to 5.0V. Good trace practices should be followed correspond-
ing to the desired operating speed. The internal circuitry of
the MD1210 is capable of operating up to 100MHz, with the
primary speed limitation being the loading effects of the load
capacitance. Because of this speed and the high transient
currents that result with capacitive loads, the bypass capaci-
tors should be as close to the chip pins as possible. The V
SS1
,
V
SS2
, and V
L
pins should have low inductance feed-through
connections directly to a ground plane. The power connec-
tions V
DD1
and V
DD2
should have a ceramic bypass capacitor
to the ground plane with short leads and decoupling compo-
nents to prevent resonance in the power leads. A common
capacitor and voltage source may be used for these two
pins, which should always have the same DC voltage ap-
plied. For applications sensitive to jitter and noise, separate
decoupling networks may be used for V
DD1
and V
DD2
.
The V
H
and V
L
pins can draw fast transient currents of up to
2.0A, so they should be provided with an appropriate bypass
capacitor located next to the chip pins. A ceramic capacitor
of up to 1.0µF may be appropriate, with a series ferrite bead
to prevent resonance in the power supply lead coming to the
capacitor. Pay particular attention to minimizing trace lengths
and using sufficient trace width to reduce inductance. Sur-
face mount components are highly recommended. Since the
output impedance of this driver is very low, in some cases it
may be desirable to add a small series resistor in series with
the output signal to obtain better waveform integrity at the
load terminals. This will of course reduce the output voltage
slew rate at the terminals of a capacitive load.
Pay particular attention to the parasitic coupling from the
driver output to the input signal terminals. This feedback
may cause oscillations or spurious waveform shapes on the
edges of signal transitions. Since the input operates with sig-
nals down to 1.2V even small coupled voltages may cause
problems. Use of a solid ground plane and good power and
signal layout practices will prevent this problem. Be careful
that the circulating ground return current from a capacitive
load cannot react with common inductance to cause noise
voltages in the input logic circuitry.
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
Name Description
IN
A
V
L
IN
B
GND
V
SS1
V
SS2
OUT
B
V
H
OUT
A
V
DD2
V
DD1
OE
Logic input. Controls OUT
A
when OE is high. Input logic high will cause the output to swing to V
L
. Input
logic low will cause the output to swing to V
H
.
Supply voltage for N-channel output stage.
Logic input. Controls OUT
B
when OE is high. Input logic high will cause the output to swing to V
L
. Input
logic low will cause the output to swing to V
H
.
Logic input ground reference.
Low side analog circuit and level shifter supply voltage. Should be at the same potential as V
SS2
.
Low side gate drive supply voltage.
Output driver. Swings from V
H
to V
L
. Intended to drive the gate of an external N-channel MOSFET via a
series capacitor. When OE is low, the output is disabled. OUT
B
will swing to V
L
turning off the external
N-channel MOSFET.
Supply voltage for P-channel output stage.
Output driver. Swings from V
H
to V
L
. Intended to drive the gate of an external P-channel MOSFET via a
series capacitor. When OE is low, the output is disabled. OUT
A
will swing to V
H
turning off the external
P-channel MOSFET.
High side gate drive supply voltage.
High side analog circuit and level shifter supply voltage. Should be at the same potential as V
DD2
.
Output-enable logic input. When OE is high, (V
OE
+ V
GND
)/2 sets the threshold transition between logic
level high and low for IN
A
and IN
B
. When OE is low, OUT
A
is at V
H
and OUT
B
is at V
L
regardless of IN
A
and IN
B
Note:
1.Thermal Pad and Pin#5 (V
SS1
) must be connected externally.
2. Index Pad and Thermal Pad are connected internally
5
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