SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max I
CC
Typical t
pd
= 14 ns
±4-mA
Output Drive at 5 V
SN54HC161 . . . J OR W PACKAGE
SN74HC161 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
Low Input Current of 1
µA
Max
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Synchronous Counting
Synchronously Programmable
SN54HC161 . . . FK PACKAGE
(TOP VIEW)
CLR
CLK
A
B
C
D
ENP
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RCO
Q
A
Q
B
Q
C
Q
D
ENT
LOAD
A
B
NC
C
D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
CLK
CLR
NC
V
CC
RCO
Q
A
Q
B
NC
Q
C
Q
D
NC − No internal connection
ORDERABLE
PART NUMBER
SN74HC161N
SN74HC161D
SN74HC161DR
SN74HC161DT
SN74HC161NSR
SN74HC161PW
SN74HC161PWR
SN74HC161PWT
SNJ54HC161J
SNJ54HC161W
SNJ54HC161FK
SNJ54HC161J
SNJ54HC161W
SNJ54HC161FK
HC161
HC161
HC161
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
description/ordering information
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed
counting designs. The ’HC161 devices are 4-bit binary counters. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed
by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output
counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK)
input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.
ORDERING INFORMATION
TA
PDIP − N
PACKAGE†
TOP-SIDE
MARKING
SN74HC161N
SOIC − D
−40°C to 85°C
SOP − NS
TSSOP − PW
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
•
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ENP
GND
NC
LOAD
ENT
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
1
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
description/ordering information (continued)
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’HC161 devices is asynchronous. A low level at the clear (CLR) input sets all four of
the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q
A
high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
LOAD
ENT
ENP
9
10
7
LD†
CK†
CLK
CLR
2
1
CK
R
LD
15
RCO
A
3
M1
G2
1, 2T/1C3
G4
3D
4R
M1
G2
1, 2T/1C3
G4
3D
4R
14
QA
13
QB
B
4
C
5
M1
G2
1, 2T/1C3
G4
3D
4R
12
QC
D
6
M1
G2
1, 2T/1C3
G4
3D
4R
11
QD
† For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
logic symbol, each D/T flip-flop
LD (Load)
TE (Toggle Enable)
CK (Clock)
M1
G2
1, 2T/1C3
G4
3D
4R
Q (Output)
D (Inverted Data)
R (Inverted Reset)
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
LD†
TG
TG
LD†
D
TG
TG
TG
CK†
CK†
TG
Q
CK†
R
† The origins of LD and CK are shown in the logic diagram of the overall device.
CK†
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54HC161, SN74HC161
4 BIT SYNCHRONOUS BINARY COUNTERS
SCLS297D − JANUARY 1996 − REVISED SEPTEMBER 2003
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (asynchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
B
C
D
CLK
ENP
ENT
QA
QB
QC
QD
RCO
12
13
14
15
0
1
2
Inhibit
Count
Sync Preset
Clear
Async
Clear
Data
Inputs
Data
Outputs
POST OFFICE BOX 655303
•
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5
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