MX98726EC
SINGLE CHIP 10/100 FAST ETHERNET
CONTROLLER WITH uP INTERFACE
1.0 Features
• Direct interface to 80188/186 up to 40Mhz.
• Integrated 10/100 TP tranceiver on chip to reduce
overall cost
• Optional MII interface for external tranceiver.
• Fully comply to IEEE 802.3u spec.
• Best fit in network printer and hub/switch manage-
ment application
• A local DMA channel between on-chip FIFOs and
packet memory
• Shared memory architecture allow host and
MX98726EC to use only one single SRAM
• Host DMA can share packet memory with local DMA
with simple hand shake protocol for x188/186 type of
processor
• Supports proprietary local DMA channel to share
packet memory
• Support bus size configuration:
- CPU : 8 bits, SRAM: 8 bits
- CPU : 16 bits, SRAM: 8/16 bits
• Flexible packet buffer partition and addressing space
for 32k, 64k up to 512K bytes
• NWAY autonegotiation function to automatically set
up network speed and protocol
• 3 loop back modes for system level diagnostics
• Rich on-chip register set to support a wide variety of
network management functions
• Support 64 bits hash table for multicast addressing
• Support software EEPROM interface for easy up-
grade of EEPROM content
• Support 1K bits and 4K bits EEPROM interface
• 5V CMOS in 128 PQFP package for minimum board
size application
1.1 Introduction
MX98726EC ( Generic MAC , or GMAC ) is a cost effec-
tive solution as a generic single chip 10/100 Fast Ethernet
controller. It is designed to directly interface 80188, 80186
( host ) without glue logic. Two types of memory sharing
schemes are supported, i.e. interleaved and shared mode
to support a variety of applications. Single chip solution
will help reduce system cost not only on the compo-
nents but also the board size. Full NWAY function with
10/100 tranceiver will ease the field installation, simply
plug the chip in and it will connect itself with the best
protocol available.
The interleaved mode allow uP to access SRAM (
packet/host buffer ) through MX98726EC's local DMA
channel. This way, no extra SRAM interface logic is
needed on the host side. If high performance is desired,
then shared memory mode is another alternative which
allow host to access SRAM on its own by denying SRAM
bus grant to MX98726EC using simple hand shake pro-
tocol. Without SRAM bus grant, MX98726EC will float
its interface connected to the SRAM, therefore host can
utilize its own memory subsystem to conduct its own
SRAM access.
A intelligent built-in SRAM bus arbitor will manage all
the SRAM access requests from host, on-chip transmit
channel and on-chip receive channel. The throughput
of these network channels and MX98726EC's DMA burst
length can be easily adjusted by option bits on the chip.
These options can help system developers to "fine tune"
a best cost/performance ratio.
MX98726EC is also equipped with fast back-to-back
transmit capability which allow software to "fire" as many
transmit packets as needed in a single command. Re-
ceive FIFO also allow back-to-back reception. Optional
EEPROM can be used to stored network network ad-
dress and other information. In case cost is really a con-
cern, most configuration options including network ad-
dress can be programmed through uP.
P/N:PM0729
REV. 1.1, MAY. 28, 2001
1
MX98726EC
2.1 Pin Description :
PIN#
82
49-54,
59-62,
76
70
Pin Name
CLKIN
AD[7:0]
AD[15:8]
ALE
A19(RXC)
Type
I, TTL
I/O, 4ma
56,57
I/O, 4ma
66-69
I,TTL
I, TTL
Description
Host Clock Input : 8M to 40 Mhz.
Multiplexed Address/Data Bit [7:0] : Internal pull-down
Multiplexed Address/Data Bit [15:8] : Internal pull-down
Address Latch Enable : Active high
Host Bus Address Bit19, when on-chip tranceiver is used,it is used in
A[19:16], when in MII mode, it is defined as receive clock RXC (25MHz or
2.5MHz) When this pin is used as address bit, it is internally grounded until
Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address
bit. Internal pull-up
Host Bus Address Bit18, when on-chip tranceiver is used,it is used in
A[19:16], when in MII mode, it is defined as receive data valid RXDV
signal. When this pin is used as address bit, it is internally grounded until
Reg50.6 (A19A16EN bit) is set to enable decoding of this pin as address
bit. Internal pull-up.
Host Bus Address Bit17, when on-chip tranceiver is used, it is used in
A[19:16], when in MII mode, it is defined as carrier same CRS signal.
When this pin isused as address bit, it is internally grounded until Reg50.6
(A19A16EN bit) is set to enable decoding of this pin as address bit. Inter-
nal pull-up.
Host Bus Address Bit16, when on-chip tranceiver is used, it is used in
A[19:16], when in MII mode, it is defined as collision COL signal. When
this pin is used as address bit, it is internally grounded until Reg50.6
(A19A16EN bit) is set to enable decoding of this pin as address bit. Inter-
nal pull-up.
Host Read Strobe: Active low. Internal pull-up
Host Write Strobe : Active low. Internal pull-up
Host Interrupt Output : Polarity can be programmed, default is active low.
For active Low interrupt application, external pull-up is reguired. For active
high interrupt application, external pull-down is required.
Host Byte High Enable : Internal pull-up.
BHEB A0
Function
0
0
Word Transfer
0
1
Upper Byte Transfer
1
0
Lower Byte Transfer
1
1
Lower Byte Transfer
Synchronous Host Ready Output : Active high synchronized to CLKIN to
indicate data is ready to be transferred. Initially low at the beginning of a
host cycle.
Chip Select : Active low, used to enable GMAC to decode host address.
When high, no host cycle is recognized by MAC.
Host Memory/IO cycle indicator : Set for memory access and reset for IO
access. Internal pull-up. Decode of MIO can be disable by DISMIO regis-
ter bit. Default is enabled.
REV. 1.1, MAY. 28, 2001
71
A18(RXDV)
I,TTL
72
A17(CRS)
I,TTL
73
A16(COL)
I,TTL
79
78
81
RDB
WRB
INTB
I, TTL
I, TTL
O/D, 4ma
75
BHEB
I,TTL
80
SRDY
O, 4ma
47
48
CSB
MIO
I, TTL
I, TTL
P/N:PM0729
5
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