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7007L25JB8

Description
Multi-Port SRAM, 32KX8, 25ns, CMOS, PQCC68
Categorystorage   
File Size164KB,21 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

7007L25JB8 Overview

Multi-Port SRAM, 32KX8, 25ns, CMOS, PQCC68

7007L25JB8 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Reach Compliance Codenot_compliant
Maximum access time25 ns
I/O typeCOMMON
JESD-30 codeS-PQCC-J68
JESD-609 codee0
memory density262144 bit
Memory IC TypeMULTI-PORT SRAM
memory width8
Humidity sensitivity level1
Number of ports2
Number of terminals68
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize32KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Filter level38535Q/M;38534H;883B
Maximum standby current0.01 A
Minimum standby current4.5 V
Maximum slew rate0.305 mA
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
Base Number Matches1
HIGH-SPEED
32K x 8 DUAL-PORT
STATIC RAM
Features
IDT7007S/L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 25/35/55ns (max.)
– Industrial: 20/25/35/55ns (max.)
– Commercial: 15/20/25/35/55ns (max.)
Low-power operation
– IDT7007S
Active: 850mW (typ.)
Standby: 5mW (typ.)
– IDT7007L
Active: 850mW (typ.)
Standby: 1mW (typ.)
IDT7007 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master,
M/S = L for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PGA and PLCC and a 80-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
A
14L
A
0L
(1,2)
I/O
0R
-I/O
7R
I/O
Control
BUSY
R
A
14R
A
0R
(1,2)
Address
Decoder
15
MEMORY
ARRAY
15
Address
Decoder
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
INT
R
(2)
2940 drw 01
JANUARY 2006
1
©2006 Integrated Device Technology, Inc.
DSC 2940/12
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