PI49FCT20807
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
1-10 Clock Buffer for
Networking Applications
Features
• High Frequency >150 MHz
• High-speed, low-noise, non-inverting 1-10 buffer
• Low-skew (<150ps) between any two output clocks
• Low duty cycle distortion <300ps
• Low propagation delay <3.5ns
• Multiple V
DD
, GND pins for noise reduction
• 2.5V supply voltage and 3V tolerant input
• Packaging (Pb-free & Green available):
-20-pin SOIC (S)
-20-pin SSOP (H)
-20-pin QSOP (Q)
Description
The PI49FCT20807, a 2.5V compatible, high-speed, low-noise 1-10
non-inverting clock buffer, is designed to target networking appli-
cations that require low-skew, low-jitter, and high-frequency clock
distribution. Providing output-to-output skew as low as 150ps, the
PI49FCT20807 is an ideal clock distribution device for synchronous
systems. Designing synchronous networking systems requires a
tight level of skew from a large number of outputs.
Pin Description
Pin Name
BUF_IN
CLK [0:9]
GND
V
DD
Input
Outputs
Ground
Power
De s cription
Block Diagram
CLK0
Pin Configuration
BUF_IN
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
VDD
CLK9
CLK8
GND
CLK7
VDD
CLK6
GND
CLK5
CLK4
CLK1
BUF_IN
CLK2
CLK0
VDD
CLK1
GND
20-Pin
H, Q, S
16
15
14
13
12
11
CLK3
CLK2
VDD
CLK3
CLK9
GND
1
PS8558B
09/24/04
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT20807
1-10 Clock Buffer for
Networking Applications
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ...................................................... –65°C to +150°C
V
DD
Voltage ...................................................................... –0.5V to +3.6V
Input/Output Voltage
(4) .......................................................
–0.5V to V
DD
+0.5V
DC Output Current ....................................................... –60mA to +60mA
Power Dissipation ........................................................................ 500mW
Note:
Stresses greater than those listed under MAXIMUM
RATINGS may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Operating Range
V
IN
Voltage ......................................................................... –0.3V to 3.6V
V
DD
Voltage ........................................................................... 2.5V ± 0.2V
Industrial Temperature .................................................... –40°C to +85°C
Input Frequency ............................................................. DC to 150 MHz
Capacitive Loading ............................................................. 10pF to 25pF
DC Electrical Characteristics
(Over the Operating Range)
Parame te rs
V
IH
V
IL
I
I
V
IK
V
OH
V
OL
De s cription
Input HIGH Voltage
Input LOW Voltage
Input Current
Clamp Diode Voltage
Output HIGH Voltage
Output LOW Voltage
Te s t Conditions
(1)
Guaranteed Logic HIGH Level (Input Pins)
Guaranteed Logic LOW Level (Input Pins)
V
DD
= Max., V
IN
= V
DD
or GND
V
DD
= Min., I
IN
= –18mA
V
DD
= Min., V
IN
= V
IH
or V
IL
V
DD
= Min., V
IN
= V
IH
or V
IL
I
OH
= –1mA
I
OH
= –8mA
I
OL
= 1mA
I
OL
= 8mA
V
IN
= V
DD
—
—
2
1.8
(3)
—
—
—
M in.
1.7
Typ.
(2)
—
—
—
–0.7
—
0.7
±1
–1
—
—
0.4
0.6
V
M ax.
Units
V
mA
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
DD
= 2.5V, +25°C ambient and maximum loading.
3. V
OH
= V
DD
– 0.6V at rated current.
4. This value is limited to 3.6V maximum.
Power Supply Characteristics
Parame te rs
I
DDQ
∆I
DD
I
DD
De s cription
Quiescent Power Supply
Current
Supply Current per
Inputs @ TTL HIGH
Dynamic Supply Current
(See Graph 1)
V
DD
= Max.
V
DD
= Max.
V
DD
= 2.7V, 15pF &
33- ohm load
Te s t Conditions
(1)
V
IN
= GND or V
DD
V
IN
= V
DD
– 0.6V
(3)
150 MHz
M in.
—
—
—
Typ.
(2)
0.1
47
136
M ax.
20
300
—
µA
Units
mA
Notes:
1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device.
2. Typical values are at V
DD
= 2.5V, +25°C ambient.
3. Per TTL driven input (V
IN
= V
DD
– 0.6V); all other inputs at V
DD
or GND.
2
PS8558B
09/24/04
Dynamic Current - IDD [mA]
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT20807
1-10 Clock Buffer for
Networking Applications
Graph 1. Dynamic Current vs. Clock Frequency
160
140
120
100
80
60
40
20
0
0
50
100
Clock Frequency [MHz]
150
200
Load = 0
Load = 15pF & 33 ohms
Capacitance
(T
A
= 25°C, f = 1 MHz)
Parame te rs
(1)
C
IN
C
O UT
De s cription
Input Capacitance
Output Capacitance
Te s t Conditions
V
IN
= 0V
V
O UT
= 0V
Typ.
3
M ax.
4
6
Units
pF
Note:
1. This parameter is determined by device characterization but is not production tested.
Switching Characteristics
(V
DD
= 2.5V ± 0.2V, T
A
= 85°C)
Parame te rs
t
R
/t
F
t
PLH
t
PHL
t
SK(o)(2)
t
SK(p)(2)
t
SK(t)(2)
De s cription
CLKn Rise/Fall Time 0.7V ~ 1.7 V
Propagation Delay BUF_IN to CLKn
Skew between two outputs of the same package
(same transition)
Skew between opposite transitions (t
PHL
- t
PLH
)
of the same output
Skew between two outputs of different package
(4)
Te s t Conditions
(1)
C
L
= 22pF, 100 MHz
C
L
= 12pF, 150 MHz
C
L
= 22pF, 100 MHz
C
L
= 12pF, 150 MHz
C
L
= 22pF, 100 MHz
C
L
= 12pF, 150 MHz
C
L
= 22pF, 100 MHz
C
L
= 12pF, 150 MHz
C
L
= 12pF, 150 MHz
M in.
–
–
–
–
–
–
–
–
–
Typ.
1.0
1.0
3.0
2.4
100
100
250
250
400
M a x.
1. 2 5
1. 2
3.5
2.7
150
150
300
300
600
ps
ns
Units
Notes:
1. See test circuit and waveforms.
2. Skew measured at worse cast temperature (max. temp).
Test Circuits for All Outputs
V
DD
V
IN
D.U.T.
C
L
V
OUT
Pulse
Generator
Definitions:
C
L
= Load capacitance: includes jig and probe capacitance.
3
PS8558B
09/24/04
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT20807
1-10 Clock Buffer for
Networking Applications
Switching Waveforms
Propagation Delay
2.5V
Input
t
PLH
Output
t
R
t
PHL
1.7V
0.7V
Pulse Skew – t
SK(P)
2.5V
Input
t
PLH
Output
t
SK(p)
= | t
PHL
– t
PLH
|
t
PHL
V
OH
1.25V
V
OL
1.25V
0V
1.25V
0V
V
OH
1.25V
V
OL
t
F
Output Skew – t
SK(O)
2.5V
Input
t
PLHx
CLKx
t
SK(o)
CLKy
t
PLHy
t
PHLy
t
SK(o)
V
OH
1.25V
V
OL
t
PHLx
V
OH
1.25V
V
OL
1.25V
0V
Package Skew – t
SK(T)
2.5V
Input
t
PLH1
Package 1
Output
t
SK(t)
Package 2
Output
t
PLH2
t
PHL2
t
SK(t)
V
OH
1.25V
V
OL
t
SK(t)
=
t
PLH2
– t
PLH1
or
t
PHL2
– t
PHL1
t
PHL1
V
OH
1.25V
V
OL
1.25V
0V
t
SK(o)
= ú t
PLHy
– t
PLHx
ú or ú t
PHLy
– t
PHLx
ú
Packaging Mechanical: 20-Pin SOIC (S)
20
.2914
.2992
7.40
7.60
.010
.029
0.254
x 45˚
0.737
1
.496 12.60
.511 12.99
.0091
.0125
0.41 .016
1.27 .050
.0926
.1043
2.35
2.65
SEATING
PLANE
.394
.419
10.00
10.65
0.23
0.32
0-8˚
.020 0.508
REF
.030 0.762
.050
BSC
1.27
.013
.020
0.33
0.51
.0040
.0118
0.10
0.30
X.XX DENOTES CONTROLLING
X.XX DIMENSIONS IN MILLIMETERS
4
PS8558B
09/24/04
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI49FCT20807
1-10 Clock Buffer for
Networking Applications
Packaging Mechanical: 20-Pin SSOP (H)
20
.197
.220
5.00
5.60
1
.272
.295
6.90
7.50
.078
2.00
Max
SEATING
PLANE
.002
Min
0.050
.004
.009
0.09
0.25
0.55 .022
0.95 .037
.291
.322
7.40
8.20
.0256
BSC
0.65
.0098
Max.
0.25
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
Packaging Mechanical: 20-Pin QSOP (Q)
20
.008
0.20
MIN.
.150
.157
3.81
3.99
Guage Plane
.008
.013
0.20
0.33
.010
0.254
1
.337 8.56
.344 8.74
Detail A
.016
.035
0.41
0.89
.041
1.04
REF
0˚-6˚
.058
REF
1.47
.053 1.35
.069 1.75
SEATING
PLANE
.015 x 45˚
0.38
Detail A
.007
.010
.016
.050
0.41
1.27
0.178
0.254
.025
BSC
0.635
.004 0.101
.010 0.254
.008 0.203
.012 0.305
.228
.244
5.79
6.19
X.XX DENOTES DIMENSIONS
X.XX IN MILLIMETERS
5
PS8558B
09/24/04
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