ASAHI KASEI
[AKD4125-A]
AKD4125-A
AK4125 Evaluation Board Rev.1
GENERAL DESCRIPTION
The AKD4125-A is an evaluation board for AK4125, the digital sample rate converter. The AKD4125-A
has the digital audio interface and can achieve the interface with digital audio system via opt-connector.
Ordering guide
AKD4125-A
---
AK4125 Evaluation Board
FUNCTION
•
DIR/DIT with optical input/output
•
10pin Header for AKM AD/DA evaluation board
5V
Opt In
AK4114
Regulator
GND
AK4114
Opt Out
COAX
COAX
10pin
Header
AK4125
10pin
Header
DSP
Data
DSP
Data
Figure 1. AKD4125-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
<KM078701>
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ASAHI KASEI
[AKD4125-A]
Operation sequence
1) Set up the power supply lines.
[VCC]
(red)
= +5V (for regulator)
[DGND]
(black)
= 0V
Each supply line should be distributed from the power supply unit.
The regulator can be supplied 3.3V to all circuits.
2) Set up the evaluation mode, jumper pins. (See the followings.)
3) Power on.
The AK4125 should be reset once bringing SW1 (PDN) “L” upon power-up.
Evaluation mode
(1) Setting for Input port
(1) When using DIR function of AK4114 (U3)
When using PORT1 (DIR) or J1 (COAX), nothing should be connected to PORT2 (INPUT).
JP2
IBICK
JP3
SDTI
JP4
ILRCK
•
SW3 setting (See Table 1)
Upper-side is “H” and lower-side is “L”.
The audio interface format of the AK4114 is fixed to 24bit, MSB justified. IDIF2-0 and PLL2-0 of SW3
should be used by default setting.
SW3 No.
1
2
3
4
5
6
7
Name
DITH
PLL2
PLL1
PLL0
IDIF0
IDIF1
IDIF2
ON (“H”)
Dither ON
OFF (“L”)
Dither OFF
Default
L
H
L
H
L
H
L
PLL Mode Setting
Fixed to default
AK4125 Audio I/F Format Setting
Fixed to default
Table 1. SW3 Setting
<KM078701>
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ASAHI KASEI
[AKD4125-A]
(2) All clocks are fed through the 10pin port
When using PORT2 (INPUT), nothing should be connected to J1 (COAX) and PORT1 (DIR).
JP2
IBICK
JP3
SDTI
JP4
ILRCK
•
SW3 setting (See Table 2)
Upper-side is “H” and lower-side is “L”.
SW3 No.
1
2
3
4
5
6
7
Name
DITH
PLL2
PLL1
PLL0
IDIF0
IDIF1
IDIF2
ON (“H”)
Dither ON
OFF (“L”)
Dither OFF
Default
L
H
L
H
L
H
L
PLL Mode Setting
Refer to Table 3
AK4125 Audio I/F Format Setting
Refer to Table 4
Table 2. SW3 Setting
Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Master / Slave
PLL2
L
L
PLL1
L
L
PLL0
L
H
ILRCK Freq
8k
∼
96kHz
8k
∼
216kHz
16k
∼
216kHz
(Note 1)
IBICK Freq
Depending on
IDIF2-0
IMCLK
Not
needed.
SMUTE
(Note 4)
Manual
Semi-Auto
Slave
IMCLK = DVSS
IBICK = Input
ILRCK = Input
Master
IMCLK = Input
IBICK = Output
ILRCK = Output
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
L
H
H
Reserved
L
L
32fsi (Note 3)
Not
L
H
64fsi
8k
∼
216kHz
needed.
(Note 2)
H
L
128fsi
64fsi
H
H
L
L
128fs
8k
∼
216kHz
L
H
256fs
8k
∼
108kHz
H
L
512fs
8k
∼
54kHz
H
H
128fs
8k
∼
216kHz
64fs
L
L
192fs
8k
∼
216kHz
L
H
384fs
8k
∼
108kHz
H
L
768fs
8k
∼
54kHz
H
H
192fs
8k
∼
216kHz
Table 3. PLL Setting (Input PORT)
Manual
Semi-Auto
Manual
Semi-Auto
Manual
Semi-Auto
Note 1. PLL lock rage is changed by the value of R and C connected FILT pin. Refer to “PLL Loop Filter” in the
datasheet. 470Ω, 0.22µF and 1nF are implemented on the evaluation board.
Note 2. The IBCIK must be continuous except when the clocks are changed.
Note 3. IBCIK = 32fsi is supported only 16bit LSB justified and I
2
S Compatible.
Note 4. Refer to “Soft Mute Operation” for Manual mode and Semi-Auto mode in the datasheet.
<KM078701>
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ASAHI KASEI
[AKD4125-A]
Mode
0
1
2
3
4
5
6
7
IDIF2
L
L
L
L
H
H
H
H
IDIF1
L
L
H
H
L
L
H
H
IDIF0
L
H
L
H
L
H
L
H
SDTI Format
16bit, LSB justified
20bit, LSB justified
24/20bit, MSB justified
24/16bit, I S Compatible
24bit, LSB justified
24bit, MSB justified
24bit, I
2
S Compatible
2
ILRCK
IBICK
Input
Input
Output
Output
IBICK Freq
≥
32fsi
≥
40fsi
≥
48fsi
≥
48fsi or
32fsi
≥
48fsi
64fs
64fs
Master / Slave
Slave
Master
Reserved
Table 4. Input Audio Interface Format (Input PORT)
(2) Setting for Output port
(1) When using DIT function of AK4114 (U4)
When using PORT4 (DIT) or J2 (TX), nothing should be connected to PORT3 (OUTPUT). When BICK and
LRCK frequencies are changed, the value of X’tal (X1) frequency should be changed.
JP6
OBICK
JP7
OLRCK
•
SW4 setting (See Table 5)
Upper-side is “H” and lower-side is “L”.
The audio interface format of the AK4114 is fixed to 24bit, MSB justified. ODIF2-0, CMODE2-0 and
OBIT1-0 of SW3 should be used by default setting.
SW4 No.
1
2
3
4
5
6
7
Name
ODIF1
ODIF0
CMODE2
CMODE1
CMODE0
OBIT1
OBIT0
ON (“H”)
OFF (“L”)
AK4125 Output Audio I/F Format Setting
Fixed to default
AK4125 Mode Setting
Fixed to default
AK4125 Output bit Length Setting
Fixed to default
Table 5. SW4 Setting
Default
H
L
H
L
L
H
H
<KM078701>
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2006/04
ASAHI KASEI
[AKD4125-A]
(2) All clocks are fed through the 10pin port
When using PORT3 (OUTPUT), nothing should be connected to J2 (TX) and PORT4 (DIT).
JP6
OBICK
JP7
OLRCK
•
SW4 setting (See Table 6)
Upper-side is “H” and lower-side is “L”.
SW4 No.
1
2
3
4
5
6
7
Name
ODIF1
ODIF0
CMODE2
CMODE1
CMODE0
OBIT1
OBIT0
ON (“H”)
OFF (“L”)
AK4125 Output Audio I/F Format Setting
Refer to Table 7
AK4125 Mode Setting
Refer to Table 8
AK4125 Output bit Length Setting
Refer to Table 9
Table 6. SW4 Setting
Default
H
L
H
L
L
H
H
Mode
ODIF1
ODIF0
SDTO Format
0
L
L
LSB justified
1
L
H
(Reserved)
2
H
L
MSB justified
3
H
H
I
2
S Compatible
Table 7. Output Audio Interface Format 1 (Output PORT)
Mode
0
1
2
3
4
5
6
7
CMODE2 CMODE1 CMODE0
Master / Slave
OMCLK
L
L
L
Master
256fso
L
L
H
Master
384fso
L
H
L
Master
512fso
L
H
H
Master
768fso
H
L
L
Slave
Not used. Set to DVSS.
H
L
H
Master
128fso
H
H
L
Master
192fso
H
H
H
Master (Bypass) Not used. Set to DVSS.
Table 8. Master/Slave Control (Output PORT)
Mode
OBIT1
OBIT0
SDTO Output
0
L
L
16bit
1
L
H
18bit
2
H
L
20bit
3
H
H
24bit
Table 9. Output Audio Interface Format 2 (Output PORT)
fso
8k
∼
108kHz
8k
∼
108kHz
8k
∼
54kHz
8k
∼
54kHz
8k
∼
216kHz
8k
∼
216kHz
8k
∼
216kHz
8k
∼
216kHz
<KM078701>
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2006/04
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