ASAHI KASEI
[AKD4394]
AKD4394
Evaluation board Rev.C for AK4394
General Description
The AKD4394 is an evaluation board for AK4394, which is 192kHz sampling 24Bit
∆Σ
DAC. The AKD4394 includes
a LPF which can add differential analog outputs from the AK4394 and also has a digital interface with AKM’s wave
generator using ROM data and AKM’s ADC evaluation boards. Therefore, it is easy to evaluate the AK4394.
Ordering Guide
AKD4394 Rev.C
--- Evaluation board Rev.C for AK4394: differential output
Function
On-board differential output buffer circuit
On-board clock generator
BNC connector for an external clock input
Compatible with 3types of interface
1.
2.
3.
Direct interface with evaluation boards for AKM’s A/D converter (AKD539X, AKD535X)
Interface with a signal generator (AKD43XX)
On-board CS8414 as DIR which accepts optical input.
Optical
Input
10pin Header
CS8414
(DIR)
2nd Order LPF
AK4394
ROM Data
or
A/D input
Lch
External
Clock
Clock
Generator
Fig.1 Block diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
Rch
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[AKD4394]
(AKD4394 Rev.C is same as AKD4393 Rev.C.)
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[AKD4394]
External Analog Circuit (Rev.C)
The differential output circuit and LPF is implemented on board. The differential outputs of AK4394 is buffered by non-inverted circuit
and output via Cannon connector(differential output). LPF adds differential outputs. NJM5534D is used for op-amp on this board that
has low noise and high voltage torelance characteristics. Analog signal is output via Cannon and BNC connectors on the board. The
output level is about 2.94Vrms(typ@VREF=5.0V) by Cannon and 2Vrms(typ@VREF=5.0V) by BNC.
+15
+
-15
47u
AOUTL- +
10n
300
300
10n
7
3
2 +
-
4
6
10u
0.1u
10u
100
430
4.7n
2
1
560
NJM5534D
+
0.1u
10u
+
220
300
0.1u
3
620
430
620
4.7n
NJM5534D
2 - 4
3 + 7
100
6
Lch
+
47u
AOUTL+ +
10n
300
300
10n
300
3
+
2 -
7
6
4
+
10u
0.1u
0.1u
10u
0.1u
+
100
560
10u
NJM5534D
220
Fig.2 External Analog Filter
Operation sequence
1. Set up the jumpers for power supply.
[JP15(REG)] selects power supply for AVDD pin of AK4394.
short:
5V is supplied from regulator. (default)
Nothing should be connected to A5V jack.
open:
5V is supplied from A5V.
2. Set up the power supply lines.
+15V=15V, -15V=-15V:
Power supply for op-amp. AVDD of AK4394 is supplied from “+15V” through regulator
(JP15: short).
A5V=5V:
This jack is used when AVDD of AK4394 is supplied from this. In this case, JP15 should be
open.
DVDD=5V:
Power supply for logic circuit on this board.
VP=3V∼5.25V:
Digital (set JP10 to VP),
AGND=DGND=0V .
Each supply line should be distributed from the power unit.
3. Set up the evaluation modes by jumper pins and DIP switches.(See next item.)
4. Power on.(The AK4394 should be reset once by bringing PD "L" upon power-up.)
*SW1 resets the AK4394 during operation.
The AK4394 is reset at SW1="L" and exits resetting at SW1="H".
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[AKD4394]
The evaluation modes and corresponding jumper pins setting
1. Evaluation Modes
•Applicable
Evaluation Mode
(1) DIR(Optical Link)
(2) Ideal sine wave generated by ROM data
(3) Using AD converted data
(4)All interface signals including master clock are fed externally.
(1) DIR(Optical Link) (default)
PORT2 is used for the evaluation using such as CD test disk. The DIR generates MCLK, BICK and LRCK SDATAfrom the
received data through optical connector(PORT2: TORX176).
JP4
JP5
VDD
INV
THR
INV
THR
XTL/EXT
DIR
DIR
XTL/EXT
2X
1X
1/2X
1X
GND
JP1
JP2
JP6
JP7
JP8
JP14
DIR
XTL
EXT
JP9
XTL
CS8414
BCP
(MSB
justified)
BCP
(others)
SD
BI
LR
CKDIV1
CKDIV2
CLK
Fig.3 Jumper set-up (DIR)
(2) Ideal sine wave generated by ROM data
Digital signal generated by AKD43XX are used. PORT1 is used for the interface with AKD43XX. Master clock is sent from
AKD4394 to AKD43XX then LRCK, BICK and SDATA are sent from AKD43XX to AKD4394.
JP1
JP2
VDD
GND
JP4
INV
THR
JP5
XTL/EXT
DIR
JP6
DIR
XTL/EXT
JP7
JP8
2X
1X
JP14
1/2X
1X
DIR
XTL
EXT
JP9
XTL
CS8414
BCP
BI
LR
SD
CKDIV1
CKDIV2
CLK
Fig.4 Jumper set-up (ROM data)
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[AKD4394]
(3) Using AD converted data
AD converted data from AKM’s AD evaluation boards(AKD539X, AKD535X) is used through PORT1.
* In case of using external clock through a BNC connector, select EXT of JP9 and short JP1.
* In case of using the double speed sampling mode, select 1/2X of JP8 and set S2-2(DFS) on.
JP1
JP2
VDD
GND
JP4
INV
THR
JP5
XTL/EXT
DIR
JP6
DIR
XTL/EXT
JP7
JP8
2X
1X
JP14
1/2X
1X
DIR
XTL
EXT
JP9
XTL
CS8414
BCP
BI
LR
SD
CKDIV1
CKDIV2
CLK
Fig.5 Jumper set-up (A/D)
(4) All interface signals including master clock are fed externally.
Under the following set-up, MCLK, LRCK and SCLK signals needed for the D/A to operate could be fed through PORT1.
JP1
JP2
VDD
GND
JP4
INV
THR
JP5
XTL/EXT
DIR
JP6
DIR
XTL/EXT
JP7
JP8
2X
1X
JP14
1/2X
1X
DIR
XTL
EXT
JP9
XTL
CS8414
BCP
SD
BI
LR
CKDIV1
CKDIV2
CLK
Fig.6 Jumper set-up (ext.)
2. MCLK set-up
When the LRCK is fed from the 74HC4040 on the board, The ratio of MCLK to LRCK can be selected by JP8 and JP14.
JP14
1X
1X
1/2X
1/2X
JP8
1X
2X
1X
2X
X'tal
12.288MHz
24.576MHz
24.576MHz
49.152MHz
MCLK
12.288MHz
24.576MHz
12.288MHz
12.288MHz
fs
48kHz
48kHz
96kHz
96kHz
MCLK/LRCK
256
512
128
128
Table.1 set-up example
3. BICK set-up
When BICK is supplied from U1(74HC4040), either 32fs or 64fs could be
selected. Fig.8 shows 64fs mode. 64fs mode is recommended.
*Only mode 0(LSB justified 16bit mode) can correspond to 32fs.
JP3
64
32
BCS
Fig.7 Jumper Set-up (BCS)
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