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71V67602S150BQI8

Description
SRAM
Categorystorage    storage   
File Size515KB,23 Pages
ManufacturerIDT (Integrated Device Technology)
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71V67602S150BQI8 Overview

SRAM

71V67602S150BQI8 Parametric

Parameter NameAttribute value
MakerIDT (Integrated Device Technology)
package instruction,
Reach Compliance Codeunknown
Base Number Matches1
256K X 36, 512K X 18
3.3V Synchronous SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs, Single Cycle Deselect
x
x
IDT71V67602
IDT71V67802
Features
256K x 36, 512K x 18 memory configurations
Supports high system speed:
– 166MHz 3.5ns clock access time
– 150MHz 3.8ns clock access time
– 133MHz 4.2ns clock access time
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW byte
GW),
GW
BWE
BW
write enable (BWE and byte writes (BW
BWE),
BWx)
3.3V core power supply
Power down controlled by ZZ input
2.5V I/O supply (V
DDQ
)
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array.
Description
The IDT71V67602/7802 are high-speed SRAMs organized as
256K x 36/512K x 18. The IDT71V676/78 SRAMs contain write, data,
address and control registers. Internal logic allows the SRAM to generate
a self-timed write based upon a decision which can be left until the end of
the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V67602/7802 can provide four cycles of
data for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will be pipelined for one
cycle before it is available on the next rising clock edge. If burst mode
operation is selected (ADV=LOW), the subsequent three cycles of output
data will be available to the user on the next three rising clock edges. The
order of these three addresses are defined by the internal burst counter
and the
LBO
input pin.
The IDT71V67602/7802 SRAMs utilize IDT’s latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
x
x
x
x
x
x
Pin Description Summary
A
0
-A
18
Address Inputs
Chip Enable
Chip Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input / Output
Core Power, I/O Power
Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Supply
Supply
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
5311 tbl 01
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
V
DD
, V
DDQ
V
SS
NOTE:
1.
BW
3
and
BW
4
are not applicable for the IDT71V67802.
FEBRUARY 2009
2003
DECEMBER
1
©2002 Integrated Device Technology, Inc.
DSC-5311/07

71V67602S150BQI8 Related Products

71V67602S150BQI8 71V67602S150BGI 71V67602S150BQI 71V67602S133BGI 71V67602S166PF 71V67602S133BQGI8 71V67602S133BQG8
Description SRAM Cache SRAM, 256KX36, 3.8ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119 Cache SRAM, 256KX36, 3.8ns, CMOS, PBGA165, 13 X 15 MM, FPBGA-165 Cache SRAM, 256KX36, 4.2ns, CMOS, PBGA119, 14 X 22 MM, PLASTIC, MS-028AA, BGA-119 Cache SRAM, 256KX36, 3.5ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP-100 SRAM SRAM
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
package instruction , 14 X 22 MM, PLASTIC, MS-028AA, BGA-119 13 X 15 MM, FPBGA-165 14 X 22 MM, PLASTIC, MS-028AA, BGA-119 14 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MO-136DJ, TQFP-100 , ,
Reach Compliance Code unknown not_compliant not_compliant not_compliant not_compliant unknown unknown
Base Number Matches 1 1 1 1 1 1 1
Is it Rohs certified? - incompatible incompatible incompatible incompatible - -
Parts packaging code - BGA BGA BGA QFP - -
Contacts - 119 165 119 100 - -
ECCN code - 3A991.B.2.A 3A991.B.2.A 3A991.B.2.A 3A991 - -
Maximum access time - 3.8 ns 3.8 ns 4.2 ns 3.5 ns - -
Other features - PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE PIPELINED ARCHITECTURE - -
Maximum clock frequency (fCLK) - 150 MHz 150 MHz 133 MHz 166 MHz - -
I/O type - COMMON COMMON COMMON COMMON - -
JESD-30 code - R-PBGA-B119 R-PBGA-B165 R-PBGA-B119 R-PQFP-G100 - -
JESD-609 code - e0 e0 e0 e0 - -
length - 22 mm 15 mm 22 mm 20 mm - -
memory density - 9437184 bit 9437184 bit 9437184 bit 9437184 bit - -
Memory IC Type - CACHE SRAM CACHE SRAM CACHE SRAM CACHE SRAM - -
memory width - 36 36 36 36 - -
Humidity sensitivity level - 3 3 3 3 - -
Number of functions - 1 1 1 1 - -
Number of terminals - 119 165 119 100 - -
word count - 262144 words 262144 words 262144 words 262144 words - -
character code - 256000 256000 256000 256000 - -
Operating mode - SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS - -
Maximum operating temperature - 85 °C 85 °C 85 °C 70 °C - -
organize - 256KX36 256KX36 256KX36 256KX36 - -
Output characteristics - 3-STATE 3-STATE 3-STATE 3-STATE - -
Package body material - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY - -
encapsulated code - BGA TBGA BGA LQFP - -
Encapsulate equivalent code - BGA119,7X17,50 BGA165,11X15,40 BGA119,7X17,50 QFP100,.63X.87 - -
Package shape - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR - -
Package form - GRID ARRAY GRID ARRAY, THIN PROFILE GRID ARRAY FLATPACK, LOW PROFILE - -
Parallel/Serial - PARALLEL PARALLEL PARALLEL PARALLEL - -
Peak Reflow Temperature (Celsius) - NOT SPECIFIED 225 NOT SPECIFIED 240 - -
power supply - 2.5,3.3 V 2.5,3.3 V 2.5,3.3 V 2.5,3.3 V - -
Certification status - Not Qualified Not Qualified Not Qualified Not Qualified - -
Maximum seat height - 2.36 mm 1.2 mm 2.36 mm 1.6 mm - -
Maximum standby current - 0.05 A 0.05 A 0.07 A 0.05 A - -
Minimum standby current - 3.14 V 3.14 V 3.14 V 3.14 V - -
Maximum slew rate - 0.325 mA 0.325 mA 0.28 mA 0.34 mA - -
Maximum supply voltage (Vsup) - 3.465 V 3.465 V 3.465 V 3.465 V - -
Minimum supply voltage (Vsup) - 3.135 V 3.135 V 3.135 V 3.135 V - -
Nominal supply voltage (Vsup) - 3.3 V 3.3 V 3.3 V 3.3 V - -
surface mount - YES YES YES YES - -
technology - CMOS CMOS CMOS CMOS - -
Temperature level - INDUSTRIAL INDUSTRIAL INDUSTRIAL COMMERCIAL - -
Terminal surface - Tin/Lead (Sn63Pb37) Tin/Lead (Sn63Pb37) Tin/Lead (Sn63Pb37) Tin/Lead (Sn85Pb15) - -
Terminal form - BALL BALL BALL GULL WING - -
Terminal pitch - 1.27 mm 1 mm 1.27 mm 0.65 mm - -
Terminal location - BOTTOM BOTTOM BOTTOM QUAD - -
Maximum time at peak reflow temperature - NOT SPECIFIED 20 NOT SPECIFIED 20 - -
width - 14 mm 13 mm 14 mm 14 mm - -
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