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71V124SA20TYGI8

Description
Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32
Categorystorage   
File Size81KB,8 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

71V124SA20TYGI8 Overview

Standard SRAM, 128KX8, 20ns, CMOS, PDSO32, 0.300 INCH, PLASTIC, SOJ-32

71V124SA20TYGI8 Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeSOJ
package instruction0.300 INCH, PLASTIC, SOJ-32
Contacts32
Reach Compliance Codeunknown
ECCN code3A991.B.2.B
Maximum access time20 ns
I/O typeCOMMON
JESD-30 codeR-PDSO-J32
JESD-609 codee3
length20.955 mm
memory density1048576 bit
Memory IC TypeSTANDARD SRAM
memory width8
Humidity sensitivity level3
Number of functions1
Number of terminals32
word count131072 words
character code128000
Operating modeASYNCHRONOUS
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
organize128KX8
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOJ
Encapsulate equivalent codeSOJ32,.34
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
Maximum seat height3.7592 mm
Maximum standby current0.01 A
Minimum standby current3 V
Maximum slew rate0.115 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
x
x
IDT71V124SA
Features
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Equal access and cycle times
– Commercial: 10/12/15/20ns
– Industrial: 10/12/15/20ns
One Chip Select plus one Output Enable pin
Inputs and outputs are LVTTL-compatible
Single 3.3V supply
Low power consumption via chip deselect
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
Description
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
as 128K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs. The JEDEC center power/GND pinout reduces
noise generation and improves system performance.
The IDT71V124 has an output enable pin which operates as fast as
5ns, with address access times as fast as 9ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
x
x
x
x
x
x
Functional Block Diagram
A
0
A
16
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O
0
- I/O
7
8
8
I/O CONTROL
.
8
WE
OE
CS
CONTROL
LOGIC
3873 drw 01
NOVEMBER 2003
1
©2003- Integrated Device Technology, Inc.
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