King Billion Electronics Co., Ltd
駿
億 電
子
股
½
有 限 公
司
KD83
LCD Driver Series
- Table of Contents -
1.
2.
3.
4.
5.
6.
6.1.
6.2.
6.3.
7.
8.
9.
10.
11.
12.
13.
General Description ___________________________________________________________________2
Features _____________________________________________________________________________2
Pin Description _______________________________________________________________________2
Pad Diagram _________________________________________________________________________3
Pad Coordination _____________________________________________________________________3
LCD Display RAM Map _______________________________________________________________4
16 Gray Scale LCD Display RAM Map _________________________________________________5
4 Gray Scale LCD Display RAM Map _________________________________________________12
Black and White LCD Display RAM Map______________________________________________15
Command Interface __________________________________________________________________17
Timing Diagram _____________________________________________________________________19
Absolute Maximum Rating ____________________________________________________________20
Recommended Operating Conditions _________________________________________________20
AC/DC Characteristics _____________________________________________________________20
Application Circuit_________________________________________________________________22
Updated History ___________________________________________________________________24
October 31, 2003
1
V1.0
King Billion Electronics Co., Ltd
駿
億 電
子
股
½
有 限 公
司
KD83
LCD Driver Series
1. General Description
KD83 is a gray-scale LCD Segment Extender which, when used with KB’s MCU with LCD Segment
Extender interface, can expand the capacity of LCD driver. It is a 16 gray-scale, 4 gray-scale, and black
and white LCD Segment Driver. This chip interfaces with KB’s MCU with provisions of Segment
Extender Interface LFR and CCK. KB’s MCUs control KD83 through a command interface. The MCU
can read/write display patterns to graphic mode display RAM by first setting up the target address,
selecting the driver configuration, and then enabling the driver. KD83 can support five different LCD
configurations: 16, 32, 48, 64 and 80 COM selectable by command register. The KD83 uses some of the
memory as display RAM, while the memory not used for display can be access as general-purpose
memory.
2. Features
Graphic mode Gray-scale LCD Display 80 segment Extender.
Command mode interface.
Support 16 gray scale, 4 gray scale and Black/White LCD display.
5 LCD Configurations: 16, 32, 48, 64, or 80 COM LCD.
Operating Range:
2.4V ~ 3.6V
Dual Port display RAM: 5K Bytes
Spare RAM for general purpose.
3. Pin Description
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
1
2
3
4
5
6
7
8
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
79
78
77
76
75
74
71
73
72
70
69
68
67
66
65
64
63
62
61
60
59
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
KD83
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG79
SEG78
SEG77
SEG76
SEG75
SEG74
SEG73
SEG72
SEG71
SEG70
58
57
56
55
54
53
52
51
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
RES_N
VDD
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
LVP
LVL5
LVL3
LVL2
LFR
CCK
REN
R_WN
D_CN
STBN
Pin # I/O
Description
41~101,
SEG[79..0]
O LCD Segment Outputs.
1~19
Charge Pump Output. These input pins must wire with master IC respectively. That
LVP
20
I means LVP with LVP, LVL5 with LVL5, …, LDL with LDL. Please refer to
application circuit.
LVL5
21
I LCD Bias Voltage 5
LVL3
22
I LCD Bias Voltage 3
LVL2
23
I LCD Bias Voltage 2
LFR
24
I LCD frame.
Pin Name
October 31, 2003
2
41
42
43
44
45
46
47
48
49
50
V1.0
King Billion Electronics Co., Ltd
駿
CCK
REN
R_WN
D_CN
STBN
GND
RD[7:0]
RES_N
VDD
25
26
27
28
29
30
31~38
39
40
I
I
I
I
I
P
B
I
億 電
子
股
½
有 限 公
司
KD83
LCD Driver Series
LCD data load
Low active Enable control for data or command register read/write.
Read(1)/write(0) mode selection.
Data(1)/Command(0) mode selection.
Active Low R/W strobe for data or command.
Power Ground Input.
8-bit bi-directional Command/Data bus with CMOS input structure.
Active low Reset input.
Positive power supply input. 0.1 µF by-pass capacitor should be added between VDD
P
and GND and placed close to the chip is necessary.
4. Pad Diagram
KD83
5. Pad Coordination
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Pad Name
SEG[18]
SEG[17]
SEG[16]
SEG[15]
SEG[14]
SEG[13]
SEG[12]
SEG[11]
SEG[10]
SEG[9]
SEG[8]
SEG[7]
SEG[6]
X-Coord. Y-Coord.
-2643
150.65
-2643
35.65
-2643
-79.35
-2643
-194.35
-2643
-309.35
-2643
-424.35
-2643
-539.35
-2643
-654.35
-2514.7
-1053.7
-2399.7
-1053.7
-2284.7
-1053.7
-2169.7
-1053.7
-2054.7
-1053.7
3
No.
52
53
54
55
56
57
58
59
60
61
62
63
64
Pad Name
SEG[68]
SEG[67]
SEG[66]
SEG[65]
SEG[64]
SEG[63]
SEG[62]
SEG[61]
SEG[60]
SEG[59]
SEG[58]
SEG[57]
SEG[56]
X-Coord. Y-Coord.
2483.45
-560.05
2483.45
-445.05
2483.45
-330.05
2483.45
-215.05
2483.45
-100.05
2483.45
14.95
2483.45
129.95
2381.3
942.1
2266.3
942.1
2151.3
942.1
2036.3
942.1
1921.3
942.1
1806.3
942.1
V1.0
October 31, 2003
King Billion Electronics Co., Ltd
駿
No.
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Pad Name
SEG[5]
SEG[4]
SEG[3]
SEG[2]
SEG[1]
SEG[0]
LVP
LVL5
LVL3
LVL2
LFR
CCK
REN
R_WN
D_CN
STBN
GND
RD[7]
RD[6]
RD[5]
RD[4]
RD[3]
RD[2]
RD[1]
RD[0]
RES_N
VDD
SEG[79]
SEG[78]
SEG[77]
SEG[76]
SEG[75]
SEG[74]
SEG[73]
SEG[72]
SEG[71]
SEG[70]
SEG[69]
億 電
子
股
½
有 限 公
Pad Name
SEG[55]
SEG[54]
SEG[53]
SEG[52]
SEG[51]
SEG[50]
SEG[49]
SEG[48]
SEG[47]
SEG[46]
SEG[45]
SEG[44]
SEG[43]
SEG[42]
SEG[41]
SEG[40]
SEG[39]
SEG[38]
SEG[37]
SEG[36]
SEG[35]
SEG[34]
SEG[33]
SEG[32]
SEG[31]
SEG[30]
SEG[29]
SEG[28]
SEG[27]
SEG[26]
SEG[25]
SEG[24]
SEG[23]
SEG[22]
SEG[21]
SEG[20]
SEG[19]
司
X-Coord. Y-Coord. No.
-1939.7
-1053.7
65
-1824.7
-1053.7
66
-1709.7
-1053.7
67
-1594.7
-1053.7
68
-1479.7
-1053.7
69
-1364.7
-1053.7
70
-1249.7
-1053.7
71
-1134.7
-1053.7
72
-1019.7
-1053.7
73
-904.7
-1053.7
74
-791.7
-1053.7
75
-680.7
-1053.7
76
-569.7
-1053.7
77
-458.7
-1053.7
78
-347.7
-1053.7
79
-236.7
-1053.7
80
-14.7
-1053.7
81
96.3
-1053.7
82
207.3
-1053.7
83
318.3
-1053.7
84
429.3
-1053.7
85
540.3
-1053.7
86
651.3
-1053.7
87
762.3
-1053.7
88
873.3
-1053.7
89
984.3
-1053.7
90
1095.3
-1053.7
91
1319.3
-1053.7
92
1434.3
-1053.7
93
1549.3
-1053.7
94
1664.3
-1053.7
95
1779.3
-1053.7
96
1894.3
-1053.7
97
2009.3
-1053.7
98
2124.3
-1053.7
99
2239.3
-1053.7 100
2354.3
-1053.7 101
2483.45
-675.05
KD83
LCD Driver Series
X-Coord. Y-Coord.
1691.3
942.1
1576.3
942.1
1461.3
942.1
1346.3
942.1
1231.3
942.1
1116.3
942.1
1001.3
942.1
886.3
942.1
771.3
942.1
656.3
942.1
541.3
942.1
426.3
942.1
311.3
942.1
196.3
942.1
81.3
942.1
-144.7
942.1
-259.7
942.1
-374.7
942.1
-489.7
942.1
-604.7
942.1
-719.7
942.1
-834.7
942.1
-949.7
942.1
-1064.7
942.1
-1179.7
942.1
-1294.7
942.1
-1409.7
942.1
-1524.7
942.1
-1639.7
942.1
-1754.7
942.1
-1869.7
942.1
-1984.7
942.1
-2099.7
942.1
-2214.7
942.1
-2329.7
942.1
-2444.7
942.1
-2559.7
942.1
6. LCD Display RAM Map
The gray-scale LCD driver can be configured to be a 16 gray-scales, 4 gray-scales or black and white
display by programming GRAY_MODE field of command register. For 4 gray-scale displays, 2-bit of
RAM is required for each pixel and 4 bit for 16 gray-scale display, 1-bit for black and white display. For
different LCD configuration, the LCD display RAM is arranged differently. The following figure shows
October 31, 2003
4
V1.0
King Billion Electronics Co., Ltd
駿
億 電
子
股
½
有 限 公
司
one byte of RAM in different LCD configurations:
0F
xx
0E
xx
0D
xx
0C
xx
0B
xx
0A
xx
09
xx
08
xx
07
xx
06
xx
05
xx
04
xx
03
xx
02
xx
KD83
LCD Driver Series
01
xx
00
xx
Black/White
4 Gray scales
16 Gray scales
Bit 7
Bit 6
Bit 5
Bit 4
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Bit 3
Bit 2
Bit 1
Bit 0
SEG3
SEG2
SEG1
SEG0
SEG1
SEG0
SEG0
The 16 Gray Scale register GRAY0 ~ GRAYF is the mapping register between the levels selected in
RAM and the real gray scale. In other words, if the content of GRAY0 is 0x03, when value of a certain
pixel is 0, the displayed effect will correspond to actual gray level 3. The 16 gray scale display use all
16 registers GRAY0 ~ GRAYF to select among 32 available gray levels to correspond to level 0 ~ 15,
while 4 gray scale display utilizes registers GRAY0 ~ GRAY3 to select among 32 gray levels to
correspond to level 0 ~ 3. Thus user can pick the gray levels which give the best and most linear effect.
6.1. 16 Gray Scale LCD Display RAM Map
Page
00
10
20
30
40
50
60
70
80
90
A0
B0
C0
D0
E0
F0
00
10
20
30
40
50
60
70
16 Gray Levels LCD Display RAM MAP
F
C
B
8 7
4 3
0
S31~S24
S23~S16 S15~S08 S07~S00
S63~S56
S55~S48 S47~S40 S39~S32
*
*
S79~S72 S71~S64
*
*
*
*
S31~S24
S23~S16 S15~S08 S07~S00
S63~S56
S55~S48 S47~S40 S39~S32
*
*
S79~S72 S71~S64
*
*
*
*
S31~S24
S23~S16 S15~S08 S07~S00
S63~S56
S55~S48 S47~S40 S39~S32
*
*
S79~S72 S71~S64
*
*
*
*
S31~S24
S23~S16 S15~S08 S07~S00
S63~S56
S55~S48 S47~S40 S39~S32
*
*
S79~S72 S71~S64
*
*
*
*
S31~S24
S23~S16 S15~S08 S07~S00
S63~S56
S55~S48 S47~S40 S39~S32
*
*
S79~S72 S71~S64
*
*
*
*
S31~S24
S23~S16 S15~S08 S07~S00
S63~S56
S55~S48 S47~S40 S39~S32
*
*
S79~S72 S71~S64
*
*
*
*
5
COM No.
COM0
COM1
0
COM2
COM3
1
COM4
COM5
October 31, 2003
V1.0
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