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7015S20J

Description
PLCC-68, Tube
Categorystorage   
File Size332KB,22 Pages
ManufacturerIDT (Integrated Device Technology)
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7015S20J Overview

PLCC-68, Tube

7015S20J Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codePLCC
package instructionPLASTIC, LCC-68
Contacts68
Manufacturer packaging codePL68
Reach Compliance Codenot_compliant
ECCN codeEAR99
Is SamacsysN
Maximum access time20 ns
Other featuresINTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
I/O typeCOMMON
JESD-30 codeS-PQCC-J68
JESD-609 codee0
length24.2062 mm
memory density73728 bit
Memory IC TypeDUAL-PORT SRAM
memory width9
Humidity sensitivity level1
Number of functions1
Number of ports2
Number of terminals68
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize8KX9
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC68,1.0SQ
Package shapeSQUARE
Package formCHIP CARRIER
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height4.57 mm
Maximum standby current0.015 A
Minimum standby current4.5 V
Maximum slew rate0.29 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width24.2062 mm
Base Number Matches1
HIGH-SPEED
8K x 9 DUAL-PORT
STATIC RAM
Features:
7015L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 12ns (max.)
Low-power operation
– IDT7015L
Active: 750mW (typ.)
Standby: 1mW (typ.)
IDT7015 easily expands data bus width to 18 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 68-pin PLCC
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
8L
I/O
Control
BUSY
L
A
12L
A
0L
(1,2)
I/O
Control
I/O
0R
-I/O
8R
BUSY
R
Address
Decoder
13
(1,2)
MEMORY
ARRAY
13
Address
Decoder
A
12R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
M/S
2954 drw 01
SEM
R
(2)
INT
R
NOTES:
1. In MASTER mode:
BUSY
is an output and is a push-pull driver
In SLAVE mode:
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull drivers.
MAY 2019
1
DSC 2954/13
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