NanoAmp Solutions, Inc.
1982 Zanker Road, San Jose, CA 95112
ph: 408-573-8878, FAX: 408-573-8877
www.nanoamp.com
EM512D16
Advance Information
EM512D16
512Kx16 bit Ultra-Low Power Asynchronous Static RAM
Overview
The EM512D16 is an integrated memory device
containing a low power 8 Mbit Static Random
Access Memory organized as 524,288 words by 16
bits. The base design is the same as NanoAmp’s
standard low voltage version, EM512W16. The
device is fabricated using NanoAmp’s advanced
CMOS process and high-speed/ultra low-power/
low-voltage circuit technology. The device pinout is
compatible with other standard 512K x 16 SRAMs.
The device is designed such that a creative user
can improve system power and performance
parameters through use of it’s unique page mode
operation.
Features
•
Dual Voltage for Optimum Performance:
Vccq - 2.3 to 3.6 Volts
Vcc - 1.7 to 2.2 Volts
Extended Temperature Range:
-40 to +85
o
C
Fast Cycle Time:
Random Access < 70 ns
Page Mode < 25 ns
Very Low Operating Current:
I
CC
< 5 mA typical at 2V, 10 Mhz
Very Low Standby Current:
I
SB
< 2 uA @ 55
o
C
16 Word Fast Page-Mode Operation
48-Pin BGA or Known Good Die available
•
•
•
•
•
•
FIGURE 1: Pin Configuration
1
A
B
C
D
E
F
G
H
LB
I/O
8
I/O
9
V
S S
2
OE
UB
I/O
10
I/O
11
3
A
0
A
3
A
5
A
17
NC
A
14
A
12
A
9
4
A
1
A
4
A
6
A
7
A
16
A
15
A
13
A
10
5
A
2
CE1
I/O
1
I/O
3
I/O
4
I/O
5
WE
A
11
6
CE2
I/O
0
I/O
2
V
CC
V
S S
I/O
6
I/O
7
NC
TABLE 1: Pin Descriptions
Pin Name
A
0
-A
18
WE
CE1, CE2
OE
UB
LB
I/O
0
-I/O
15
V
CC
V
CCQ
V
SS
NC
Pin Function
Address Inputs
Write Enable Input
Chip Enable Inputs
Output Enable Input
Upper Byte Enable Input
Lower Byte Enable Input
Data Inputs/Outputs
Power
Power I/O pins only
Ground
Not Connected
V
CCQ
I/O
12
I/O
14
I/O
15
A
18
I/O
13
NC
A
8
48 Pin BGA (top)
FIGURE 1: Typical Operating Envelope (Serial R/W Mix)
12.5
10.0
(mA)
Typical I
CC
7.5
2.0 Volts
5.0
2.5
0.0
0
2.5
5.0
7.5
10.0
12.5
15.0
Operating Frequency (Mhz)
Stock No. 23144-B 3/01
Advance - Subject to Change Without Notice
1
EM512D16
NanoAmp Solutions, Inc.
FIGURE 3: Functional Block Diagram
Advance Information
Address
Inputs
A
0
- A
3
Word
Address
Decode
Logic
W
o
r
d
M
u
x
Input/
Output
Mux
and
Buffers
Address
Inputs
A
4
- A
18
Page
Address
Decode
Logic
32K Page
x 16 Word
x 16 bit
RAM Array
I/O
0
- I/O
7
I/O
8
- I/O
15
CE1
CE2
WE
OE
UB
LB
Control
Logic
TABLE 2: Functional Description
CE1
H
X
X
L
L
L
CE2
X
L
X
H
H
H
WE
X
X
X
L
H
H
OE
X
X
X
X
3
L
H
UB
X
X
H
L
1
L
1
L
1
LB
X
X
H
L
1
L
1
L
1
I/O
0
- I/O
15 1
High Z
High Z
High Z
Data In
Data Out
High Z
MODE
Standby
2
Standby
2
Standby
2
Write
3
Read
Active
POWER
Standby
Standby
Standby
Active
Active
Active
1. When UB and LB are in select mode (low), I/O
0
- I/O
15
are affected as shown. When LB only is in the select mode only I/O
0
- IO
7
are affected as shown. When UB is in the select mode only I/O
8
- I/O
15
are affected as shown. If both UB and LB are in the dese-
lect mode (high), the chip is in a standby mode.
2. When the device is in standby mode, control inputs (WE, O E, UB, and LB), address inputs and data input/outputs are internally
isolated from any external influence and disabled from exerting any influence externally.
3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit.
TABLE 3: Capacitance*
Item
Input Capacitance
I/O Capacitance
Symbol
C
IN
C
I/O
Test Condition
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
V
IN
= 0V, f = 1 MHz, T
A
= 25
o
C
Min
Max
8
8
Unit
pF
pF
Note: These parameters are verified in device characterization and are not 100% tested
Stock No. 23144-B 3/01
Advance - Subject to Change Without Notice
2
EM512D16
NanoAmp Solutions, Inc.
TABLE 4: Absolute Maximum Ratings*
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Storage Temperature
Operating Temperature
*
Advance Information
Symbol
V
IN,OUT
V
CC
T
STG
T
A
Rating
–0.3 to V
CC
+0.3
–0.3 to 3.0
–40 to 125
–-40 to +85
Unit
V
V
o
o
C
C
Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operating section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 5: Operating Characteristics (Over specified Temperature Range)
Item
Supply Voltage
Supply Voltage I/O Only
Minimum Data Retention Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Output Leakage Current
Read/Write Operating Supply Cur-
rent @ 1 uS Cycle Time
Random Access Operating Supply
Current @ 70 nS Cycle Time
Page Mode Operating Supply Cur-
rent @ 25 nS Cycle Time
Read/Write Quiescent Operating
Supply Current (Note 2)
Symbol
V
CC
V
CCQ
V
DR
V
IH
V
IL
V
OH
V
O L
I
LI
I
LO
I
CC1
I
CC2
I
CC2
I
OH
= 0.2mA
I
OL
= -0.2mA
V
IN
= 0 to V
CC
OE = V
IH
or Chip Disabled
VCC=2.2 V, V
IN
=V
IH
or V
IL
Chip Enabled, IOL = 0
VCC=2.2 V, V
IN
=V
IH
or V
IL
Chip Enabled, IOL = 0
VCC=2.2 V, V
IN
=V
IH
or V
IL
Chip Enabled, IOL = 0
V
IN
= V
CC
or 0V
Chip Enabled, IOL = 0 f = 0,
t
A
= 85
o
C, VCC = 3.6 V
V
IN
= V
CC
or 0V
Chip Disabled
t
A
= 55
o
C, VCC = 2.2 V
V
IN
= V
CC
or 0V
Chip Disabled
t
A
= 85
o
C, VCC = 2.2 V
Vcc = 1.2V, V
IN
= V
CC
or 0
Chip Disabled, t
A
= 85
o
C
Chip Disabled (Note 2)
Test Conditions
Min
1.7
2.3
1.2
0.7V
CC
–0.5
V
CC
–0.2
0.2
0.5
0.5
2.0
15.0
7.0
V
CC
+0.5
0.3V
CC
Typ
Max
2.2
3.6
Unit
V
V
V
V
V
V
V
uA
uA
mA
mA
mA
I
CC3
2.0
mA
Operating Standby Current
(Note 2)
Maximum Standby Current
(Note 2)
Maximum Data Retention Current
(Note 2)
I
SB1
2
uA
I
SB2
20
uA
I
DR
5
uA
1. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). It will also go into a standby mode whenever
if both UB and LB are high. In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS.
2. The Chip is Disabled when CE1 is high or CE2 is low. The Chip is Enabled when CE1 is low and CE2 is high.
Stock No. 23144-B 3/01
Advance - Subject to Change Without Notice
3
EM512D16
NanoAmp Solutions, Inc.
TABLE 6: Timing Test Conditions
Item
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Levels
Operating Temperature
0.1V
CC
to 0.9 V
CC
5ns
0.5 V
CC
-40 to +85
o
C
Advance Information
TABLE 7: Timing
Item
Read Cycle Time
Address Access Time (Random Access)
Address Access Time (Word Mode)
Chip Enable to Valid Output
Output Enable to Valid Output
Byte Select to Valid Output
Chip Enable to Low-Z output
Output Enable to Low-Z Output
Byte Select to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Byte Select Disable to High-Z Output
Output Hold from Address Change
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Select to End of Write
Write Pulse Width
Address Setup Time
Write Recovery Time
Write to High-Z Output
Data to Write Time Overlap
Data Hold from Write Time
End Write to Low-Z Output
Symbol
t
RC
t
AA
t
AAW
t
CO
t
O E
t
LB
, t
UB
t
LZ
t
OLZ
t
LBZ
, t
UBZ
t
HZ
t
OHZ
t
LBHZ
, t
UBHZ
t
OH
t
WC
t
CW
t
AW
t
LBW
, t
UBW
t
WP
t
AS
t
WR
t
WHZ
t
DW
t
DH
t
OW
40
0
5
10
5
10
0
0
0
10
85
50
40
50
40
0
0
20
40
0
5
20
20
20
V
CCQ =
2.3 - 3.6 V
Min.
85
85
85
85
30
85
10
5
10
0
0
0
10
70
50
40
50
40
0
0
20
20
20
20
Max.
V
CCQ =
2.7 - 3.6 V
Min.
70
70
70
70
25
70
Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Stock No. 23144-B 3/01
Advance - Subject to Change Without Notice
4
EM512D16
NanoAmp Solutions, Inc.
FIGURE 4: Timing of Read Cycle (1) (CE = OE = V
IL
, WE
=
V
IH
)
t
RC,
t
RCW
Address
t
AA,
t
AAW
t
OH
Advance Information
Data Out
Previous Data Valid
Data Valid
FIGURE 5: Timing Waveform of Read Cycle (2) (WE
=
V
IH
)
t
RC,
t
RCW
Address
t
AA,
t
AAW
t
HZ(1,2)
CE1
t
C O
CE2
t
LZ(2)
t
OE
OE#
t
OLZ
t
LB,
t
UB
LB , UB
t
LBLZ,
t
UBLZ
High-Z
Data Out
t
LBHZ,
t
UBHZ
Data Valid
t
OHZ(1)
Stock No. 23144-B 3/01
Advance - Subject to Change Without Notice
5
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