70V3319S133BFG datasheet, PDF - EEWORLD Datasheet

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70V3319S133BFG: DescriptionDual-Port SRAM, 256KX18, 4.2ns, CMOS, CBGA208, 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208; Categorystorage storage; File Size238KB，23 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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70V3319S133BFG Overview

Dual-Port SRAM, 256KX18, 4.2ns, CMOS, CBGA208, 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208

70V3319S133BFG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	LFBGA, BGA208,17X17,32
Contacts	208
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Is Samacsys	N
Maximum access time	4.2 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz
I/O type	COMMON
JESD-30 code	S-CBGA-B208
JESD-609 code	e1
length	15 mm
memory density	4718592 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	208
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX18
Output characteristics	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	LFBGA
Encapsulate equivalent code	BGA208,17X17,32
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	2.5/3.3,3.3 V
Certification status	Not Qualified
Maximum seat height	1.7 mm
Maximum standby current	0.03 A
Minimum standby current	3.15 V
Maximum slew rate	0.4 mA
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	30
width	15 mm
Base Number Matches	1

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LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

HIGH-SPEED 3.3V

IDT70V3319/99S

256/128K x 18

SYNCHRONOUS

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

– Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output mode

LVTTL- compatible, single 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz.

Available in a 128-pin Thin Quad Flatpack, 208-pin fine

pitch Ball Grid Array, and 256-pin Ball

Grid Array

Supports JTAG features compliant to IEEE 1149.1

– Due to limited pin count, JTAG is not supported on the

128-pin TQFP package

Green parts available, see ordering information

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

– Due to limited pin count PL/

option is not supported

on the 128-pin TQFP package. Device is pipelined

outputs only on each port.

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (6Gbps bandwidth)

– Fast 3.6ns clock to data out

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

– Data input, address, byte enable and control registers

◆

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B

1 0

R R

1/0

R/W

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

1b 0b 1a 0a

0a 1a 0b 1b

0/1

FT/PIPE

0/1

256K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

CLK

17L(1)

REPEAT

ADS

CNTEN

CLK

17R(1)

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

5623 tbl 01

NOTE:

1. A

is a NC for IDT70V3399.

TDI

JTAG

TDO

TCK

TMS

TRST

JUNE 2018

DSC

5623/11

70V3319S133BFG Related Products

	70V3319S133BFG	70V3399S133PRFG	70V3399S133PRFGI	70V3319S133BCG	70V3399S133BCGI	70V3319S133BFGI	70V3319S133PRFG
Description	Dual-Port SRAM, 256KX18, 4.2ns, CMOS, CBGA208, 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208	Dual-Port SRAM, 128KX18, 4.2ns, CMOS, PQFP128, 14 X 20 MM X 1.4 MM, GREEN, PLASTIC, TQFP-128	Dual-Port SRAM, 128KX18, 4.2ns, CMOS, PQFP128, 14 X 20 MM X 1.4 MM, GREEN, PLASTIC, TQFP-128	Dual-Port SRAM, 256KX18, 4.2ns, CMOS, CBGA256, 17 X 17 MM X 1.4 MM, 1 MM PITCH, GREEN, BGA-256	Dual-Port SRAM, 128KX18, 4.2ns, CMOS, CBGA256, 17 X 17 MM X 1.4 MM, 1 MM PITCH, GREEN, BGA-256	Dual-Port SRAM, 256KX18, 4.2ns, CMOS, CBGA208, 15 X 15 MM X 1.4 MM, 0.80 MM PITCH, GREEN, FPBGA-208	Dual-Port SRAM, 256KX18, 4.2ns, CMOS, PQFP128, 14 X 20 MM X 1.4 MM, GREEN, PLASTIC, TQFP-128
Is it lead-free?	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	conform to	conform to	conform to	conform to	conform to	conform to
Maker	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Parts packaging code	BGA	QFP	QFP	BGA	BGA	BGA	QFP
package instruction	LFBGA, BGA208,17X17,32	LFQFP, QFP128,.63X.87	LFQFP, QFP128,.63X.87	LBGA, BGA256,16X16,40	LBGA, BGA256,16X16,40	LFBGA, BGA208,17X17,32	LFQFP, QFP128,.63X.87
Contacts	208	128	128	256	256	208	128
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN code	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
Maximum access time	4.2 ns	4.2 ns	4.2 ns	4.2 ns	4.2 ns	4.2 ns	4.2 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz
I/O type	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 code	S-CBGA-B208	R-PQFP-G128	R-PQFP-G128	S-CBGA-B256	S-CBGA-B256	S-CBGA-B208	R-PQFP-G128
JESD-609 code	e1	e3	e3	e1	e1	e1	e3
length	15 mm	20 mm	20 mm	17 mm	17 mm	15 mm	20 mm
memory density	4718592 bit	2359296 bit	2359296 bit	4718592 bit	2359296 bit	4718592 bit	4718592 bit
Memory IC Type	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM
memory width	18	18	18	18	18	18	18
Humidity sensitivity level	3	3	3	3	3	3	3
Number of functions	1	1	1	1	1	1	1
Number of ports	2	2	2	2	2	2	2
Number of terminals	208	128	128	256	256	208	128
word count	262144 words	131072 words	131072 words	262144 words	131072 words	262144 words	262144 words
character code	256000	128000	128000	256000	128000	256000	256000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	85 °C	70 °C	85 °C	85 °C	70 °C
organize	256KX18	128KX18	128KX18	256KX18	128KX18	256KX18	256KX18
Output characteristics	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
Package body material	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	CERAMIC, METAL-SEALED COFIRED	PLASTIC/EPOXY
encapsulated code	LFBGA	LFQFP	LFQFP	LBGA	LBGA	LFBGA	LFQFP
Encapsulate equivalent code	BGA208,17X17,32	QFP128,.63X.87	QFP128,.63X.87	BGA256,16X16,40	BGA256,16X16,40	BGA208,17X17,32	QFP128,.63X.87
Package shape	SQUARE	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE	SQUARE	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
Parallel/Serial	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
Peak Reflow Temperature (Celsius)	260	260	260	260	260	260	260
power supply	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.7 mm	1.6 mm	1.6 mm	1.7 mm	1.7 mm	1.7 mm	1.6 mm
Maximum standby current	0.03 A	0.03 A	0.04 A	0.03 A	0.04 A	0.04 A	0.03 A
Minimum standby current	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
Maximum slew rate	0.4 mA	0.4 mA	0.48 mA	0.4 mA	0.48 mA	0.48 mA	0.4 mA
Maximum supply voltage (Vsup)	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V
Minimum supply voltage (Vsup)	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
Nominal supply voltage (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
surface mount	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)	Matte Tin (Sn) - annealed	Matte Tin (Sn) - annealed	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Matte Tin (Sn) - annealed
Terminal form	BALL	GULL WING	GULL WING	BALL	BALL	BALL	GULL WING
Terminal pitch	0.8 mm	0.5 mm	0.5 mm	1 mm	1 mm	0.8 mm	0.5 mm
Terminal location	BOTTOM	QUAD	QUAD	BOTTOM	BOTTOM	BOTTOM	QUAD
Maximum time at peak reflow temperature	30	30	30	30	30	30	30
width	15 mm	14 mm	14 mm	17 mm	17 mm	15 mm	14 mm
Base Number Matches	1	1	1	1	1	1	1

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