Rev: 102607
DS3102
Stratum 3 Timing Card IC with
Synchronous Ethernet Support
General Description
The DS3102 is a low-cost, feature-rich timing IC for
telecom timing cards. With 8 input clocks, the device
directly accepts both line timing from a large number of
line cards and external timing from external DS1/E1
BITS transceivers. The DS3102 continually monitors all
input clocks and performs automatic
hitless reference
switching if the primary reference fails.
The T0 DPLL
complies with the Stratum 3 requirements of GR-1244,
GR-253, and the requirements of G.813 and G.8262.
The highly programmable DS3102 support numerous
input
and output frequencies including rates required
Features
♦
Synchronization for Stratum 3/4E/4, SMC, and
SEC
♦
♦
♦
♦
♦
♦
Meets Requirements of GR-1244 Stratum 3,
GR-253, G.812 Type IV, G.813, and G.8262
Stratum 3 Holdover Accuracy with Suitable
External Oscillator
Programmable Bandwidth: 0.5mHz to 400Hz
Hitless Reference Switching on Loss of Input
Automatic or Manual Phase Build-Out
Frequency Conversion Among SONET/SDH,
PDH, Ethernet, Wireless, and CMTS Rates
Four CMOS/TTL Inputs (≤ 125MHz)
Four LVDS/LVPECL/CMOS/TTL Inputs
(≤ 156.25MHz)
Three Optional Frame-Sync Inputs (CMOS/TTL)
Continuous Input Clock Quality Monitoring
Numerous Input Clock Frequencies Supported:
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
Ethernet xMII: 2.5, 25, 125, 156.25MHz
PDH: N x DS1, N x E1, N x DS2, DS3, E3
Frame Sync: 2kHz, 4kHz, 8kHz
Custom: Any Multiple of 2kHz Up to 131.072MHz,
Any Multiple of 8kHz Up to 155.52MHz
Three CMOS/TTL Outputs (≤ 125MHz)
Two LVDS/LVPECL Outputs (≤ 312.50MHz)
Two Dual CMOS/TTL and LVDS/LVPECL Outputs
Five CMOS Outputs Have Additional Output Pins
That Can Be Powered at 2.5V or 3.3V
Numerous Output Clock Frequencies Supported:
SONET/SDH: 6.48, N x 19.44, N x 51.84MHz
Ethernet xMII: 2.5, 25, 125, 156.25, 312.5MHz
PDH: N x DS1, N x E1, N x DS2, DS3, E3
Other: 10, 10.24, 13, 30.72MHz
Frame Sync: 2kHz, 8kHz
Custom Clock Rates: Any Multiple of 2kHz Up to
77.76MHz, Any Multiple of 8kHz Up to
311.04MHz, Any Multiple of 10kHz Up to
388.79MHz
Internal Compensation for Master Clock
Oscillator
SPI™ Processor Interface
1.8V Operation with 3.3V I/O (5V Tolerant)
Industrial Temperature Range
Maxim Integrated Products
for SONET/SDH, Synchronous Ethernet (1G, 10G,
and 100Mbps), wireless base stations, and CMTS
systems. PLL bandwidths from 0.5mHz to 400Hz are
supported, and a wide variety of PLL characteristics
and device features can be configured to meet the
needs of many different applications.
Two DS3102
devices can be configured in a master/slave
arrangement for timing card equipment protection.
The DS3102 register set is backward compatible with
Semtech’s ACS8522 timing card IC. The DS3102 has a
different package and pin arrangement than the
ACS8522.
♦
8 Input Clocks
♦
♦
♦
♦
♦
♦
7 Output Clocks
♦
♦
♦
♦
♦
Applications
SONET/SDH Equipment Clocks (SECs)
Synchronous Ethernet Equipment Clocks (EECs)
Timing Card IC in WAN Equipment Including MSPPs,
Ethernet Switches, Routers, DSLAMs, and
Wireless Base Stations
PART
DS3102GN
DS3102GN+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
81 CSBGA (10mm)
2
81 CSBGA (10mm)
2
Ordering Information
+Denotes
a lead-free/RoHS-compliant package.
♦
SPI is a trademark of Motorola, Inc.
General
♦
♦
♦
♦
1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of
any device may be simultaneously available through various sales channels. For information about device errata, go to:
www.maxim-ic.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or
visit Maxim’s website at www.maxim-ic.com.
____________________________________________________________________________________________ DS3102
Table of Contents
1.
2.
3.
4.
5.
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6.
7.
7.1
7.2
7.3
7.4
7.5
STANDARDS COMPLIANCE ..........................................................................................................6
APPLICATION EXAMPLE ...............................................................................................................7
BLOCK DIAGRAM ...........................................................................................................................8
DETAILED DESCRIPTION ..............................................................................................................9
DETAILED FEATURES .................................................................................................................11
I
NPUT
C
LOCK
F
EATURES
...............................................................................................................11
T0 DPLL F
EATURES
.....................................................................................................................11
T4 DPLL F
EATURES
.....................................................................................................................11
O
UTPUT
APLL F
EATURES
.............................................................................................................12
O
UTPUT
C
LOCK
F
EATURES
............................................................................................................12
R
EDUNDANCY
F
EATURES
..............................................................................................................12
G
ENERAL
F
EATURES
.....................................................................................................................12
PIN DESCRIPTIONS ......................................................................................................................13
FUNCTIONAL DESCRIPTION .......................................................................................................17
O
VERVIEW
....................................................................................................................................17
D
EVICE
I
DENTIFICATION AND
P
ROTECTION
.....................................................................................18
L
OCAL
O
SCILLATOR AND
M
ASTER
C
LOCK
C
ONFIGURATION
.............................................................18
I
NPUT
C
LOCK
C
ONFIGURATION
......................................................................................................19
Signal Format Configuration ................................................................................................................ 19
Frequency Configuration...................................................................................................................... 20
Frequency Monitoring .......................................................................................................................... 21
Activity Monitoring ................................................................................................................................ 21
Selected Reference Activity Monitoring ............................................................................................... 22
Priority Configuration............................................................................................................................ 23
Automatic Selection Algorithm ............................................................................................................. 23
Forced Selection .................................................................................................................................. 24
Ultra-Fast Reference Switching ........................................................................................................... 24
External Reference Switching Mode.................................................................................................... 24
Output Clock Phase Continuity During Reference Switching .............................................................. 25
T0 DPLL State Machine ....................................................................................................................... 27
T4 DPLL State Machine ....................................................................................................................... 30
Bandwidth ............................................................................................................................................ 32
Damping Factor.................................................................................................................................... 32
Phase Detectors................................................................................................................................... 32
Loss-of-Lock Detection ........................................................................................................................ 33
Phase Build-Out ................................................................................................................................... 34
Input to Output (Manual) Phase Adjustment........................................................................................ 34
Phase Recalibration ............................................................................................................................. 34
Frequency and Phase Measurement................................................................................................... 35
Input Jitter and Wander Tolerance....................................................................................................... 36
Jitter and Wander Transfer .................................................................................................................. 36
Output Jitter and Wander ..................................................................................................................... 37
Signal Format Configuration ................................................................................................................ 38
Frequency Configuration...................................................................................................................... 38
7.4.1
7.4.2
7.5.1
7.5.2
7.5.3
I
NPUT
C
LOCK
M
ONITORING
............................................................................................................21
7.6
I
NPUT
C
LOCK
P
RIORITY
, S
ELECTION
,
AND
S
WITCHING
....................................................................23
7.6.1
7.6.2
7.6.3
7.6.4
7.6.5
7.6.6
7.7
DPLL A
RCHITECTURE AND
C
ONFIGURATION
..................................................................................26
7.7.1
7.7.2
7.7.3
7.7.4
7.7.5
7.7.6
7.7.7
7.7.8
7.7.9
7.7.10
7.7.11
7.7.12
7.7.13
7.8
7.9
O
UTPUT
C
LOCK
C
ONFIGURATION
...................................................................................................37
E
QUIPMENT
R
EDUNDANCY
C
ONFIGURATION
...................................................................................45
2 of 141
7.8.1
7.8.2
Rev: 102607
____________________________________________________________________________________________ DS3102
7.9.1
7.9.2
7.9.3
7.9.4
Master-Slave Output Clock-Phase Alignment ..................................................................................... 45
Master-Slave Frame and Multiframe Alignment with the External Frame-Sync Signals ..................... 46
SYNCn Pins ......................................................................................................................................... 47
Other Configuration Options ................................................................................................................ 48
7.10
7.11
7.12
7.13
8.
8.1
8.2
8.3
8.4
9.
9.1
9.2
9.3
9.4
10.
10.1
10.2
10.3
10.4
10.5
10.6
11.
12.
13.
14.
M
ICROPROCESSOR
I
NTERFACE
..................................................................................................48
R
ESET
L
OGIC
.............................................................................................................................52
P
OWER
-S
UPPLY
C
ONSIDERATIONS
.............................................................................................52
I
NITIALIZATION
............................................................................................................................52
S
TATUS
B
ITS
.................................................................................................................................53
C
ONFIGURATION
F
IELDS
................................................................................................................53
M
ULTIREGISTER
F
IELDS
.................................................................................................................53
R
EGISTER
D
EFINITIONS
.................................................................................................................54
REGISTER DESCRIPTIONS .........................................................................................................53
JTAG TEST ACCESS PORT AND BOUNDARY SCAN .............................................................123
JTAG D
ESCRIPTION
....................................................................................................................123
JTAG TAP C
ONTROLLER
S
TATE
M
ACHINE
D
ESCRIPTION
.............................................................124
JTAG I
NSTRUCTION
R
EGISTER AND
I
NSTRUCTIONS
......................................................................126
JTAG T
EST
R
EGISTERS
..............................................................................................................127
ELECTRICAL CHARACTERISTICS............................................................................................128
DC C
HARACTERISTICS
.............................................................................................................128
I
NPUT
C
LOCK
T
IMING
...............................................................................................................132
O
UTPUT
C
LOCK
T
IMING
............................................................................................................132
SPI I
NTERFACE
T
IMING
............................................................................................................133
JTAG I
NTERFACE
T
IMING
.........................................................................................................135
R
ESET
P
IN
T
IMING
...................................................................................................................136
PIN ASSIGNMENTS ....................................................................................................................137
PACKAGE INFORMATION .........................................................................................................139
ACRONYMS AND ABBREVIATIONS .........................................................................................140
DATA SHEET REVISION HISTORY............................................................................................141
Rev: 102607
3 of 141
____________________________________________________________________________________________ DS3102
List of Figures
Figure 2-1. Typical Application Example ..................................................................................................................... 7
Figure 3-1. Block Diagram ........................................................................................................................................... 8
Figure 7-1. DPLL Block Diagram ............................................................................................................................... 26
Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 28
Figure 7-3. T4 DPLL State Transition Diagram ......................................................................................................... 31
Figure 7-4. FSYNC 8kHz Options.............................................................................................................................. 44
Figure 7-5. SPI Clock Phase Options ........................................................................................................................ 50
Figure 7-6. SPI Bus Transactions.............................................................................................................................. 51
Figure 9-1. JTAG Block Diagram............................................................................................................................. 123
Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 125
Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 130
Figure 10-2. Recommended Termination for LVPECL Signals on LVDS Input Pins .............................................. 130
Figure 10-3. Recommended Termination for LVPECL-Compatible Output Pins .................................................... 131
Figure 10-4. SPI Interface Timing Diagram ............................................................................................................. 134
Figure 10-5. JTAG Timing Diagram......................................................................................................................... 135
Figure 10-6. Reset Pin Timing Diagram .................................................................................................................. 136
Figure 11-1. Pin Assignment Diagram..................................................................................................................... 138
Rev: 102607
4 of 141
____________________________________________________________________________________________ DS3102
List of Tables
Table 1-1. Applicable Telecom Standards................................................................................................................... 6
Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 13
Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 14
Table 6-3. Global Pin Descriptions ............................................................................................................................ 15
Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 15
Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 16
Table 6-6. Power-Supply Pin Descriptions ................................................................................................................ 16
Table 7-1. GR-1244 Stratum 3 Stability Requirements Example .............................................................................. 18
Table 7-2. Input Clock Capabilities ............................................................................................................................ 19
Table 7-3. Locking Frequency Modes ....................................................................................................................... 20
Table 7-4. Default Input Clock Priorities .................................................................................................................... 23
Table 7-5. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 32
Table 7-6. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode .......................................................... 36
Table 7-7. Output Clock Capabilities ......................................................................................................................... 37
Table 7-8. Digital1 Frequencies................................................................................................................................. 39
Table 7-9. Digital2 Frequencies................................................................................................................................. 40
Table 7-10. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) ........................................................ 40
Table 7-11. T0 APLL Frequency Configuration ......................................................................................................... 40
Table 7-12. T0 APLL2 Frequency Configuration ....................................................................................................... 40
Table 7-13. T4 APLL Frequency Configuration ......................................................................................................... 41
Table 7-14. OC1 to OC7 Output Frequency Selection .............................................................................................. 41
Table 7-15. Standard Frequencies for Programmable Outputs ................................................................................ 42
Table 7-16. Equipment Redundancy Methodology ................................................................................................... 45
Table 7-17. External Frame-Sync Source ................................................................................................................. 48
Table 8-1. Register Map ............................................................................................................................................ 54
Table 9-1. JTAG Instruction Codes ......................................................................................................................... 126
Table 9-2. JTAG ID Code ........................................................................................................................................ 127
Table 10-1. Recommended DC Operating Conditions ............................................................................................ 128
Table 10-2. DC Characteristics................................................................................................................................ 128
Table 10-3. CMOS/TTL Pins ................................................................................................................................... 129
Table 10-4. LVDS/LVPECL Input Pins .................................................................................................................... 129
Table 10-5. LVDS Output Pins ................................................................................................................................ 129
Table 10-6. LVPECL Level-Compatible Output Pins............................................................................................... 130
Table 10-7. Input Clock Timing................................................................................................................................ 132
Table 10-8. Input Clock to Output Clock Delay ....................................................................................................... 132
Table 10-9. Output Clock Phase Alignment, Frame-Sync Alignment Mode............................................................ 132
Table 10-10. SPI Interface Timing ........................................................................................................................... 133
Table 10-11. JTAG Interface Timing........................................................................................................................ 135
Table 10-12. Reset Pin Timing ................................................................................................................................ 136
Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 137
Table 12-1. CSBGA Package Thermal Properties, Natural Convection ................................................................. 139
Rev: 102607
5 of 141
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