DS26556
4-Port Cell/Packet Over T1/E1/J1
Transceiver
www.maxim-ic.com
GENERAL DESCRIPTION
The DS26556 is a quad, software-selectable T1, E1,
or J1 transceiver with a cell/packet/TDM interface. It is
composed of four framer/formatters + LIUs, and a
UTOPIA (cell), POS-PHY™ (packet), and TDM
backplane interface. Each framer has an HDLC
controller that can be mapped to any DS0 or FDL
(T1)/Sa (E1) bit. The DS26556 also includes full-
featured BERT devices per port, and an internal clock
adapter useful for creating synchronous, high-
frequency backplane timing. The DS26556 is
controlled through an 8-bit parallel port that can be
configured for nonmultiplexed Intel or Motorola
operation.
FEATURES
Four Independent, Full-Featured T1/E1/J1
Transceivers
UTOPIA 2 and 3 Cell Interface
POS-PHY 2 and 3 Packet Interface
TDM Backplane Supports TDM Bus Rates
from 1.544MHz to 16.384MHz
Alarm Detection and Insertion
Full-Featured BERT for Each Port
AMI, B8ZS, HDB3, NRZ Line Coding
Transmit Synchronizer
APPLICATIONS
Routers
Add-Drop Multiplexers
DSLAMs
PBXs
Switches
Central Office Equipment
POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
IMA
ATM
WAN Interface
Customer-Premise
Equipment
BOC Message Controller (T1)
One HDLC Controller per Framer
Performance Monitor Counters
RAI-CI and AIS-CI Support
Internal Clock Generator (CLAD) Supplies
16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
JTAG Test Port
Single 3.3V Supply with 5V Tolerant Inputs
17mm x 17mm, 256-Pin CSBGA (1.00mm
Pitch)
ORDERING INFORMATION
PART
DS26556
DS26556N
TEMP RANGE
0°C to +70°C
-40°C to +85°C
PIN-
PACKAGE
256 CSBGA
256 CSBGA
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
1
REV: 120407
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
TABLE OF CONTENTS
1
2
BLOCK DIAGRAMS
10
FEATURES
11
2.1 F
RAMER
/LIU ................................................................................................................................................11
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
Framer/Formatter ................................................................................................................................................11
Line Interface (LIU) .............................................................................................................................................11
Clock Synthesizer ...............................................................................................................................................12
HDLC Controllers ................................................................................................................................................12
Test and Diagnostics...........................................................................................................................................12
General ...............................................................................................................................................................12
ATM ....................................................................................................................................................................13
HDLC ..................................................................................................................................................................13
2.2
C
ELL
/P
ACKET
I
NTERFACE
.............................................................................................................................12
2.2.1
2.2.2
2.2.3
2.3 C
ONTROL
P
ORT
...........................................................................................................................................13
3
BACKPLANE CONFIGURATION SCENARIOS
15
4
5
ACRONYMS AND GLOSSARY
19
PIN DESCRIPTIONS
20
5.1 S
HORT
P
IN
L
IST
...........................................................................................................................................20
5.2 D
ETAILED
P
IN
L
IST
.......................................................................................................................................24
6
DEVICE CONFIGURATION
32
7
FUNCTIONAL PIN TIMING
33
7.1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................................................33
7.2 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
...............................................................................................34
7.3 UTOPIA/POS-PHY/SPI-3 S
YSTEM
I
NTERFACE
F
UNCTIONAL
T
IMING
.............................................................36
7.3.1
7.3.2
7.3.3
7.3.4
UTOPIA Level 2 Functional Timing .....................................................................................................................36
UTOPIA Level 3 Functional Timing .....................................................................................................................40
POS-PHY Level 2 Functional Timing ..................................................................................................................43
POS-PHY Level 3 Functional Timing ..................................................................................................................47
8
FUNCTIONAL DESCRIPTION
49
8.1 C
ELL
/ P
ACKET
I
NTERFACE
D
ESCRIPTION
......................................................................................................49
8.1.1
8.1.2
Reset Descriptions ..............................................................................................................................................49
BIT / BYTE Ordering ...........................................................................................................................................49
General Description ............................................................................................................................................49
Features..............................................................................................................................................................50
System Interface Bus Controller .........................................................................................................................50
General Description ............................................................................................................................................54
Features..............................................................................................................................................................54
Transmit Cell/Packet Processor ..........................................................................................................................55
Receive Cell/Packet Processor ...........................................................................................................................55
Cell Processor.....................................................................................................................................................56
Packet Processor ................................................................................................................................................61
FIFO....................................................................................................................................................................63
System Loopback................................................................................................................................................64
T1 Loopbacks .....................................................................................................................................................65
H.100 (CT Bus) Compatibility..............................................................................................................................66
T1 Receive Status and Information .....................................................................................................................67
Receive AIS-CI and RAI-CI Detection.................................................................................................................69
T1 Receive-Side Digital Milliwatt Code Generation.............................................................................................69
T1 Error Count Registers ....................................................................................................................................69
T1 Receive Signaling Operation..........................................................................................................................70
Software Signaling ..............................................................................................................................................70
Hardware Signaling.............................................................................................................................................70
Signaling Re-insertion .........................................................................................................................................70
Receive Signaling Freeze ...................................................................................................................................71
Fractional T1 Support (Gapped-Clock Mode) .....................................................................................................71
T1 Bit-Oriented Code (BOC) Controller...............................................................................................................71
8.2
UTOPIA/POS-PHY/SPI-3 S
YSTEM
I
NTERFACE
............................................................................................49
8.2.1
8.2.2
8.2.6
8.3
ATM C
ELL
/ HDLC P
ACKET
P
ROCESSING
.....................................................................................................54
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.4
T1 R
ECEIVE
F
RAMER
D
ESCRIPTION AND
O
PERATION
.....................................................................................65
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.4.6
8.4.7
8.4.8
8.4.9
8.4.10
8.4.11
8.4.12
8.4.13
Rev: 120407
2 of 370
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
8.4.14
8.4.15
8.4.16
8.4.17
8.4.18
Receive SLC-96 Operation .................................................................................................................................71
Receive FDL .......................................................................................................................................................71
Programmable In-Band Loop-Code Detection ....................................................................................................72
Receive HDLC Controller....................................................................................................................................72
Receive HDLC Controller Example .....................................................................................................................73
T1 Per-Channel Loopback ..................................................................................................................................74
T1 Transmit DS0 Monitoring Function.................................................................................................................74
T1 Transmit Signaling Operation.........................................................................................................................74
T1 Transmit Per-Channel Idle Code Insertion .....................................................................................................75
T1 Transmit Channel Mark Registers..................................................................................................................75
Fractional T1 Support (Gapped Clock Mode)......................................................................................................75
T1 Transmit Bit Oriented Code (BOC) Controller ................................................................................................75
T1 Transmit FDL .................................................................................................................................................75
Transmit SLC–96 Operation ...............................................................................................................................76
Transmit HDLC Controller...................................................................................................................................76
HDLC Transmit Example ....................................................................................................................................76
Programmable In-Band Loop-Code Generator ...................................................................................................77
Interfacing the T1 Tx Formatter to the BERT ......................................................................................................78
T1 Transmit Synchronizer ...................................................................................................................................78
H.100 (CT Bus) Compatibility..............................................................................................................................78
E1 Error Count Registers ....................................................................................................................................79
DS0 Monitoring Function.....................................................................................................................................80
E1 Receive Signaling Operation .........................................................................................................................80
Fractional E1 Support (Gapped Clock Mode) .....................................................................................................81
Additional Sa-Bit and Si-Bit Receive Operation (E1 Mode) .................................................................................81
HDLC Overhead Control Receive Example ........................................................................................................81
Interfacing the E1 Rx Framer to the BERT..........................................................................................................82
E1 Transmit Formatter Description and Operation..............................................................................................83
Automatic Alarm Generation ...............................................................................................................................83
G.706 Intermediate CRC-4 Updating (E1 Mode Only) ........................................................................................83
E1 Transmit DS0 Monitoring Function ................................................................................................................84
E1 Transmit Signaling Operation ........................................................................................................................84
Fractional E1 Support (Gapped Clock Mode) .....................................................................................................85
Additional (Sa) and International (Si) Bit Operation (E1 Mode) ...........................................................................85
E1 Transmit HDLC Controller .............................................................................................................................85
E1 HDLC Transmit Example ...............................................................................................................................86
Interfacing the E1 Transmitter to the BERT ........................................................................................................87
E1 Transmit Synchronizer ...................................................................................................................................87
8.5
T1 T
RANSMIT
F
ORMATTER
D
ESCRIPTION AND
O
PERATION
.............................................................................74
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
8.5.10
8.5.11
8.5.12
8.5.13
8.5.14
8.6
E1 R
ECEIVE
F
RAMER
D
ESCRIPTION AND
O
PERATION
.....................................................................................78
8.6.1
8.6.2
8.6.3
8.6.4
8.6.5
8.6.6
8.6.7
8.6.8
8.6.9
8.6.10
8.6.11
8.6.12
8.6.13
8.6.14
8.6.15
8.6.16
8.6.17
8.6.18
8.6.19
9
LINE INTERFACE UNIT (LIU)
88
9.1 LIU T
RANSMITTER
........................................................................................................................................88
9.1.1 Pulse Shapes
...................................................................................................................................................88
9.1.2 Transmit Termination
......................................................................................................................................88
9.1.3 Power-Down and High-Z
................................................................................................................................88
9.1.4 Transmit All Ones
............................................................................................................................................88
9.1.5 Driver Fail Monitor
...........................................................................................................................................88
9.2 R
ECEIVER
....................................................................................................................................................91
9.2.1 Receiver Monitor Mode
...................................................................................................................................91
9.2.2 Peak Detector and Slicer
................................................................................................................................91
9.2.3 Clock and Data Recovery
...............................................................................................................................91
9.2.4 Receive Level Indicator
..................................................................................................................................91
9.2.5 Loss of Signal
...................................................................................................................................................92
9.3 J
ITTER
A
TTENUATOR
....................................................................................................................................94
9.4 LIU L
OOPBACKS
...........................................................................................................................................95
9.4.1
9.4.2
9.4.3
Analog Loopback ................................................................................................................................................95
Local Loopback ...................................................................................................................................................95
Remote Loopback ...............................................................................................................................................95
10
11
OVERALL REGISTER MAP
96
REGISTER MAPS AND DESCRIPTIONS
98
11.1 G
LOBAL
R
EGISTERS
.....................................................................................................................................98
11.1.1
Global Control Registers .....................................................................................................................................98
Rev: 120407
3 of 370
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.1.2
11.2.1
11.2.2
11.2.3
11.2.4
11.2.5
11.2.6
11.2.7
11.2.8
11.3.1
11.3.2
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
11.4.7
11.4.8
11.4.9
11.4.10
11.4.11
11.4.12
11.4.13
11.4.14
11.4.15
11.4.16
11.4.17
Global Status Registers ....................................................................................................................................105
General Cell / Packet Registers ........................................................................................................................112
Cell/Packet Status Registers.............................................................................................................................114
Transmit FIFO Registers...................................................................................................................................116
Transmit Cell Processor Registers....................................................................................................................121
Transmit Packet Processor Registers ...............................................................................................................129
Receive Cell Processor Registers.....................................................................................................................135
Receive Packet Processor Registers ................................................................................................................150
Receive FIFO Registers....................................................................................................................................162
Transmit System Interface Registers ................................................................................................................165
Receive System Interface Registers .................................................................................................................168
Receive Master-Mode Register.........................................................................................................................174
Interrupt Information Register ...........................................................................................................................175
T1 Receive Control Registers ...........................................................................................................................176
T1 Line-Code Violation Count Register (LCVCR) .............................................................................................192
T1 Path-Code Violation Count Register (PCVCR) ............................................................................................193
T1 Frames Out-of-Sync Count Register (FOSCR) ............................................................................................194
DS0 Monitoring Function...................................................................................................................................195
Receive Signaling Registers .............................................................................................................................196
T1 Receive Per-Channel Idle Code Insertion ....................................................................................................199
T1 Receive Channel Mark Registers.................................................................................................................200
Receive Fractional T1 Support (Gapped-Clock Mode)......................................................................................201
Receive T1 Bit-Oriented Code (BOC) Controller...............................................................................................202
Receive SLC-96 Operation ...............................................................................................................................203
Receive FDL .....................................................................................................................................................204
Programmable In-Band Loop-Code Detection ..................................................................................................205
Receive HDLC Controller..................................................................................................................................211
Receive BERT ..................................................................................................................................................217
11.2 C
ELL
/P
ACKET
R
EGISTER
D
ESCRIPTIONS
.....................................................................................................111
11.3 S
YSTEM
I
NTERFACE
R
EGISTERS
..................................................................................................................165
11.4 R
ECEIVE
T1 F
RAMER
R
EGISTERS
...............................................................................................................171
11.5 T1 T
RANSMIT FRAMER
................................................................................................................................219
11.5.1 Transmit-Master Mode Register........................................................................................................................222
11.5.2 Interrupt Information Registers..........................................................................................................................222
11.5.3 T1 Transmit Control Registers ..........................................................................................................................223
11.5.4 T1 Transmit Status and Information ..................................................................................................................228
11.5.5 T1 Per-Channel Loopback ................................................................................................................................231
11.5.6 T1 Transmit DS0 Monitoring Function...............................................................................................................232
11.5.7 T1 Transmit Signaling Operation.......................................................................................................................232
11.5.8 T1 Transmit Per-Channel Idle Code Insertion ...................................................................................................236
11.5.9 T1 Transmit Channel Mark Registers................................................................................................................238
11.5.10 Fractional T1 Support (Gapped Clock Mode)....................................................................................................240
11.5.11 T1 Transmit Bit Oriented Code (BOC) Controller ..............................................................................................240
11.5.12 T1 Transmit FDL ...............................................................................................................................................242
11.5.13 Transmit SLC–96 Operation .............................................................................................................................242
11.5.14 Transmit HDLC Controller.................................................................................................................................243
Transmit Interrupt Mask Register 2 .................................................................................................................................248
11.5.15 Programmable In-Band Loop-Code Generator .................................................................................................250
11.5.16 Interfacing the T1 Tx Formatter to the BERT ....................................................................................................252
11.5.17 T1 Transmit Synchronizer .................................................................................................................................254
11.6 E1 R
ECEIVE
F
RAMER
.................................................................................................................................256
11.6.1
11.6.2
11.6.3
11.6.4
11.6.5
11.6.6
11.6.7
11.6.8
11.6.9
11.6.10
11.6.11
11.6.12
11.6.13
11.6.14
E1 Receive Framer Description and Operation.................................................................................................259
Receive Master Mode Register .........................................................................................................................259
Interrupt Information Registers..........................................................................................................................261
E1 Receive Control Registers ...........................................................................................................................261
E1 Receive Status and Information...................................................................................................................266
E1 Error Count Registers ..................................................................................................................................277
DS0 Monitoring Function...................................................................................................................................280
E1 Receive Signaling Operation .......................................................................................................................281
E1 Receive Per-Channel Idle Code Insertion....................................................................................................283
E1 Receive Channel Mark Registers ................................................................................................................284
Fractional E1 Support (Gapped Clock Mode) ...................................................................................................285
Additional Sa-Bit and Si-Bit Receive Operation (E1 Mode) ...............................................................................286
Receive Framer HDLC Controller .....................................................................................................................292
Interfacing the E1 Rx Framer to the BERT........................................................................................................299
Rev: 120407
4 of 370
DS26556 4-Port Cell/Packet Over T1/E1/J1 Transceiver
11.7 E1 T
RANSMIT
F
RAMER
...............................................................................................................................301
11.7.1
11.7.2
11.7.3
11.7.4
11.7.5
11.7.6
11.7.7
11.7.8
11.7.9
11.7.10
11.7.11
11.7.12
11.7.13
11.7.14
Transmit Master Mode Register ........................................................................................................................304
Interrupt Information Registers..........................................................................................................................305
E1 Transmit Control Registers ..........................................................................................................................305
E1 Transmit Status and Information..................................................................................................................309
Per-Channel Loopback .....................................................................................................................................310
E1 Transmit DS0 Monitoring Function ..............................................................................................................311
E1 Transmit Signaling Operation ......................................................................................................................312
E1 Transmit Per-Channel Idle Code Insertion...................................................................................................316
E1 Transmit Channel Mark Registers ...............................................................................................................317
Fractional E1 Support (Gapped Clock Mode) ...................................................................................................318
Additional (Sa) and International (Si) Bit Operation (E1 Mode) .........................................................................318
E1 Transmit HDLC Controller ...........................................................................................................................325
Interfacing the E1 Transmitter to the BERT ......................................................................................................331
E1 Transmit Synchronizer .................................................................................................................................332
LINE INTERFACE UNIT (LIU)
334
12.1 LIU R
EGISTERS
..........................................................................................................................................334
13 BIT ERROR RATE TESTER (BERT)
341
13.1 BERT R
EGISTER
B
IT
D
ESCRIPTIONS
...........................................................................................................342
14 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
349
14.1 TAP C
ONTROLLER
S
TATE
M
ACHINE
............................................................................................................350
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
14.1.10
14.1.11
14.1.12
14.1.13
14.1.14
14.1.15
14.1.16
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
14.3.1
14.3.2
14.3.3
Test-Logic-Reset...............................................................................................................................................351
Run-Test-Idle ....................................................................................................................................................351
Select-DR-Scan ................................................................................................................................................351
Capture-DR.......................................................................................................................................................351
Shift-DR ............................................................................................................................................................351
Exit1-DR............................................................................................................................................................351
Pause-DR .........................................................................................................................................................351
Exit2-DR............................................................................................................................................................351
Update-DR ........................................................................................................................................................351
Select-IR-Scan..................................................................................................................................................351
Capture-IR ........................................................................................................................................................352
Shift-IR ..............................................................................................................................................................352
Exit1-IR .............................................................................................................................................................352
Pause-IR ...........................................................................................................................................................352
Exit2-IR .............................................................................................................................................................352
Update-IR..........................................................................................................................................................352
SAMPLE/PRELOAD .........................................................................................................................................353
BYPASS............................................................................................................................................................353
EXTEST ............................................................................................................................................................353
CLAMP..............................................................................................................................................................353
HIGHZ...............................................................................................................................................................353
IDCODE ............................................................................................................................................................353
Boundary Scan Register ...................................................................................................................................354
Bypass Register ................................................................................................................................................354
Identification Register........................................................................................................................................354
12
14.2 I
NSTRUCTION
R
EGISTER
.............................................................................................................................353
14.3 T
EST
R
EGISTERS
........................................................................................................................................354
15
16
PIN ASSIGNMENT
355
PACKAGE INFORMATION
356
16.1 256-B
ALL
TE-CSBGA (56-G6028-001).....................................................................................................356
17 THERMAL INFORMATION
357
18
19
ABSOLUTE MAXIMUM RATINGS
358
AC TIMING
359
19.1 T
RANSMIT
TDM P
ORT
AC C
HARACTERISTICS
.............................................................................................361
19.2 R
ECEIVE
TDM P
ORT
AC C
HARACTERISTICS
...............................................................................................362
19.3 H
IGH
-S
PEED
P
ORT
AC C
HARACTERISTICS
..................................................................................................363
19.4 S
YSTEM
I
NTERFACE
AC C
HARACTERISTICS
.................................................................................................364
19.5 M
ICROPROCESSOR
B
US
AC C
HARACTERISTICS
...........................................................................................366
19.6 JTAG I
NTERFACE
T
IMING
...........................................................................................................................369
5 of 370
Rev: 120407
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