PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
LIFE SUPPORT POLICY
Pericom Semiconductor Corporation’s products are not authorized for use as critical components in life support devices or systems
unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of PSC.
1)
Life support devices or system are devices or systems which:
a) Are intended for surgical implant into the body or
b) Support or sustain life and whose failure to perform, when properly used in accordance with instructions for use provided
in the labeling, can be reasonably expected to result in a significant injury to the user.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to
cause the failure of the life support device or system, or to affect its safety or effectiveness. Pericom Semiconductor Corporation
reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or
performance and to supply the best possible product. Pericom Semiconductor does not assume any responsibility for use of any
circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no
representations that circuitry described herein is free from patent infringement or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Pericom
Semiconductor Corporation.
2)
All other trademarks are of their respective companies.
Page 2 of 108
APRIL 2006 – Revision 2.02
06-0044
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
REVISION HISTORY
Date
03/26/03
05/14/03
Revision Number
1.00
1.01
Description
First Release of Data Sheet
Correction to description for bit[0] at offset 48h. Changed from Memory Read Flow
Through Disable to Memory Read Flow Through
Enable.
Added reset condition to offset 4Ch, bits [31:28]
Revised descriptions and added ordering information for PI7C8150B-33 (33MHz) device
06/10/03
1.02
Revised temperature support to industrial temperature
Revised temperature support back to extended commercial range (0C to 85C)
06/25/03
1.03
Corrected pin descriptions for S_M66EN, P_M66EN, and S_CLKOUT.
Corrected MS0 and MS1 pin assignments on Table 2.4. MS0 should be B14 and MS1
should be R16.
07/31/03
1.031
Added PBGA pin assignments to signal descriptions in Section 2.2.
Revised power consumption specifications in section 17.6
Revised TDELAY specifications in sections 17.4 and 17.5
Modified spacing on a few chapters. No changes to content.
Corrected VDD and VSS pin assignments on Table 2.2.7. Removed pins 106 and 155
(R16 and B14) as these should be MS1 and MS0 respectively.
Added Industrial temp and Pb-free parts in the Ordering Information
Added Ambient Temperature spec for PI7C8150BI
Added industrial temp and Pb-free descriptions to the features section in the introduction
Revised register description bits[31:24] offset 18h - Secondary Latency Timer Register
(section 14.1.13)
Revised register description for bits[3:2] offset 48h – Extended Chip Control Register
(section 14.1.31)
Corrected configuration register offset 80h (bit[15:0] is secondary bus master timeout
counter and bit[31:16] is primary bus master timeout counter)
Revised and added further descriptions for bit[15:0] offset 80h and bit[31:16] offset 80h
Corrected Note 4 to show REQ_L has a setup time of 12ns and GNT_L has a setup time
of 10ns (section 17.3)
Removed ‘Advance Information’ title from headers
Removed email (solutions@pericom.com) link
Revised PCI Local Bus specification compliance to 2.3
10/20/03
02/13/04
05/20/04
07/06/04
1.04
1.05
1.06
1.061
08/12/04
1.07
09/23/04
2.00
01/10/05
2.01
04/05/06
2.02
Page 3 of 108
APRIL 2006 – Revision 2.02
06-0044
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
TABLE OF CONTENTS
1
2
INTRODUCTION .............................................................................................................................. 11
SIGNAL DEFINITIONS ................................................................................................................... 12
2.1
S
IGNAL
T
YPES
............................................................................................................................... 12
2.2
S
IGNALS
........................................................................................................................................ 12
2.2.1
PRIMARY BUS INTERFACE SIGNALS
.......................................................................... 12
2.2.3
CLOCK SIGNALS
............................................................................................................... 15
2.2.4
MISCELLANEOUS SIGNALS...........................................................................................
16
2.2.5
GENERAL PURPOSE I/O INTERFACE SIGNALS
........................................................ 17
2.2.6
JTAG BOUNDARY SCAN SIGNALS
................................................................................ 17
2.2.7
POWER AND GROUND.....................................................................................................
18
2.3
PIN LIST – 208-PIN FQFP .......................................................................................................... 18
2.4
PIN LIST – 256-BALL PBGA ..................................................................................................... 20
3
PCI BUS OPERATION ..................................................................................................................... 22
3.1
TYPES OF TRANSACTIONS..................................................................................................... 22
3.2
SINGLE ADDRESS PHASE ....................................................................................................... 23
3.3
DEVICE SELECT (DEVSEL_L) GENERATION ...................................................................... 23
3.4
DATA PHASE ............................................................................................................................. 23
3.5
WRITE TRANSACTIONS .......................................................................................................... 23
3.5.1
MEMORY WRITE TRANSACTIONS................................................................................
24
3.5.2
MEMORY WRITE AND INVALIDATE
............................................................................ 25
3.5.3
DELAYED WRITE TRANSACTIONS...............................................................................
25
3.5.4
WRITE TRANSACTION ADDRESS BOUNDARIES.......................................................
26
3.5.5
BUFFERING MULTIPLE WRITE TRANSACTIONS.....................................................
26
3.5.6
FAST BACK-TO-BACK TRANSACTIONS
....................................................................... 27
3.6
READ TRANSACTIONS............................................................................................................ 27
3.6.1
PREFETCHABLE READ TRANSACTIONS....................................................................
27
3.6.2
NON-PREFETCHABLE READ TRANSACTIONS..........................................................
27
3.6.3
READ PREFETCH ADDRESS BOUNDARIES
............................................................... 28
3.6.4
DELAYED READ REQUESTS
.......................................................................................... 28
3.6.5
DELAYED READ COMPLETION WITH TARGET
........................................................ 29
3.6.6
DELAYED READ COMPLETION ON INITIATOR BUS................................................
29
3.6.7
FAST BACK-TO-BACK READ TRANSACTION
............................................................. 30
3.7
CONFIGURATION TRANSACTIONS ...................................................................................... 30
3.7.1
TYPE 0 ACCESS TO PI7C8150B.......................................................................................
31
3.7.2
TYPE 1 TO TYPE 0 CONVERSION
.................................................................................. 31
3.7.3
TYPE 1 TO TYPE 1 FORWARDING.................................................................................
33
3.7.4
SPECIAL CYCLES
............................................................................................................. 33
3.8
TRANSACTION TERMINATION ............................................................................................. 34
3.8.1
MASTER TERMINATION INITIATED BY PI7C8150B
................................................. 35
3.8.2
MASTER ABORT RECEIVED BY PI7C8150B
................................................................ 36
3.8.3
TARGET TERMINATION RECEIVED BY PI7C8150B..................................................
36
3.8.4
TARGET TERMINATION INITIATED BY PI7C8150B..................................................
38
4
ADDRESS DECODING..................................................................................................................... 40
4.1
ADDRESS RANGES ................................................................................................................... 40
4.2
I/O ADDRESS DECODING........................................................................................................ 40
4.2.1
I/O BASE AND LIMIT ADDRESS REGISTER................................................................
41
4.2.2
ISA MODE...........................................................................................................................
42
Page 5 of 108
APRIL 2006 – Revision 2.02
06-0044
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