74LVC1G10GW datasheet, PDF - EEWORLD Datasheet

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74LVC1G10GW: DescriptionSingle 3-input NAND gate; Categorylogic logic; File Size63KB，14 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74LVC1G10GW Overview

Single 3-input NAND gate

74LVC1G10GW Parametric

Parameter Name	Attribute value
Source Url Status Check Date	2013-06-14 00:00:00
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SOT-363
package instruction	PLASTIC, SC-88, SOT-363, 6 PIN
Contacts	6
Reach Compliance Code	compli
series	LVC/LCX/Z
JESD-30 code	R-PDSO-G6
JESD-609 code	e3
length	2 mm
Load capacitance (CL)	50 pF
Logic integrated circuit type	NAND GATE
MaximumI(ol)	0.024 A
Humidity sensitivity level	1
Number of functions	1
Number of entries	3
Number of terminals	6
Maximum operating temperature	125 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	TSSOP
Encapsulate equivalent code	TSSOP6,.08
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
method of packing	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Su	6.2 ns
propagation delay (tpd)	21.5 ns
Certification status	Not Qualified
Schmitt trigger	NO
Maximum seat height	1.1 mm
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	1.65 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	AUTOMOTIVE
Terminal surface	Tin (Sn)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	1.25 mm
Base Number Matches	1

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74LVC1G10

Single 3-input NAND gate

Rev. 01 — 2 October 2007

Product data sheet

1. General description

The 74LVC1G10 provides a low-power, low-voltage single 3-input NAND gate.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of

this device in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

time.

This device is fully speciﬁed for partial power-down applications using I

OFF

The I

OFF

circuitry disables the output, preventing the damaging backﬂow current through

the device when it is powered down.

2. Features

Wide supply voltage range from 1.65 V to 5.5 V

High noise immunity

Complies with JEDEC standard:

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V).

±24

mA output drive (V

= 3.0 V)

CMOS low power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

ESD protection:

HBM JESD22-A114E exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101-C exceeds 1000 V

Multiple package options

Speciﬁed from

−40 °C

to +85

°C

and

−40 °C

to +125

°C

74LVC1G10GW Related Products

	74LVC1G10GW	74LVC1G10	74LVC1G10GM	74LVC1G10GV	74LVC1G10GF
Description	Single 3-input NAND gate	Single 3-input NAND gate	Single 3-input NAND gate	Single 3-input NAND gate	Single 3-input NAND gate
Source Url Status Check Date	2013-06-14 00:00:00	-	2013-06-14 00:00:00	2013-06-14 00:00:00	2013-06-14 00:00:00
Is it lead-free?	Lead free	-	Lead free	Lead free	Lead free
Is it Rohs certified?	conform to	-	conform to	conform to	conform to
Maker	NXP	-	NXP	NXP	NXP
Parts packaging code	SOT-363	-	SON	TSOP	SON
package instruction	PLASTIC, SC-88, SOT-363, 6 PIN	-	VSON, SOLCC6,.04,20	PLASTIC, SC-74, SOT-457, TSOP-6	VSON, SOLCC6,.04,14
Contacts	6	-	6	6	6
Reach Compliance Code	compli	-	compli	compli	compli
series	LVC/LCX/Z	-	LVC/LCX/Z	LVC/LCX/Z	LVC/LCX/Z
JESD-30 code	R-PDSO-G6	-	R-PDSO-N6	R-PDSO-G6	S-PDSO-N6
JESD-609 code	e3	-	e3	e3	e3
length	2 mm	-	1.45 mm	2.9 mm	1 mm
Load capacitance (CL)	50 pF	-	50 pF	50 pF	50 pF
Logic integrated circuit type	NAND GATE	-	NAND GATE	NAND GATE	NAND GATE
MaximumI(ol)	0.024 A	-	0.024 A	0.024 A	0.024 A
Humidity sensitivity level	1	-	1	1	1
Number of functions	1	-	1	1	1
Number of entries	3	-	3	3	3
Number of terminals	6	-	6	6	6
Maximum operating temperature	125 °C	-	125 °C	125 °C	125 °C
Minimum operating temperature	-40 °C	-	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TSSOP	-	VSON	TSSOP	VSON
Encapsulate equivalent code	TSSOP6,.08	-	SOLCC6,.04,20	TSOP6,.11,37	SOLCC6,.04,14
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	SQUARE
Package form	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	-	SMALL OUTLINE, VERY THIN PROFILE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, VERY THIN PROFILE
method of packing	TAPE AND REEL	-	TAPE AND REEL	TAPE AND REEL	TAPE AND REEL
Peak Reflow Temperature (Celsius)	260	-	260	260	260
power supply	3.3 V	-	3.3 V	3.3 V	3.3 V
Prop。Delay @ Nom-Su	6.2 ns	-	6.2 ns	6.2 ns	6.2 ns
propagation delay (tpd)	21.5 ns	-	21.5 ns	21.5 ns	21.5 ns
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified
Schmitt trigger	NO	-	NO	NO	NO
Maximum seat height	1.1 mm	-	0.5 mm	1.1 mm	0.5 mm
Maximum supply voltage (Vsup)	5.5 V	-	5.5 V	5.5 V	5.5 V
Minimum supply voltage (Vsup)	1.65 V	-	1.65 V	1.65 V	1.65 V
Nominal supply voltage (Vsup)	1.8 V	-	1.8 V	1.8 V	1.8 V
surface mount	YES	-	YES	YES	YES
technology	CMOS	-	CMOS	CMOS	CMOS
Temperature level	AUTOMOTIVE	-	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE
Terminal surface	Tin (Sn)	-	Tin (Sn)	Tin (Sn)	Tin (Sn)
Terminal form	GULL WING	-	NO LEAD	GULL WING	NO LEAD
Terminal pitch	0.65 mm	-	0.5 mm	0.95 mm	0.35 mm
Terminal location	DUAL	-	DUAL	DUAL	DUAL
Maximum time at peak reflow temperature	30	-	30	30	30
width	1.25 mm	-	1 mm	1.5 mm	1 mm
Base Number Matches	1	-	1	1	1

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