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Intel 82870P2 PCI/PCI-X 64-bit
Hub 2 (P64H2)
Datasheet
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January 2003
Document Number:
290732-002
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Information in this document is provided in connection with Intel
®
products. No license, express or implied, by estoppel or otherwise, to any intellectual
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The Intel
®
PCI/PCI-X 64-bit Hub 2 (P64H2) may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
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Copyright © 2003, Intel Corporation
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Intel 82870P2 P64H2 Datasheet
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Contents
1
Introduction ....................................................................................................................... 17
1.1
1.2
2
Related Documents.............................................................................................. 17
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Intel P64H2 Overview ......................................................................................... 17
Signal Description ............................................................................................................. 19
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Hub Interface........................................................................................................ 21
PCI Bus Interface 64-bit Extension ...................................................................... 25
PCI Bus Interface Clocks and Reset.................................................................... 27
Interrupt Interface ................................................................................................. 28
Hot Plug Interface................................................................................................. 29
SMBus Interface................................................................................................... 31
Miscellaneous Signals.......................................................................................... 31
Power and Reference Voltage Signals
................................................................. 32
Pin Straps............................................................................................................. 32
3
Register Description.......................................................................................................... 34
3.1
3.2
Register Nomenclature and Access Attributes..................................................... 35
Hub Interface-to-PCI Bridge PCI Configuration Registers (Device 31 and 29).... 36
3.2.1
VID—Vendor ID Register (D29,31: F0) ................................................ 38
3.2.2
DID—Device ID Register (D29,31: F0)................................................. 38
3.2.3
PD_CMD—PCI Primary Device Command Register (D29,31: F0) ..... 38
3.2.4
PD_STS—PCI Primary Device Status Register (D29,31: F0) .............. 40
3.2.5
RID—Revision ID Register (D29,31: F0) .............................................. 41
3.2.6
CC—Class Code Register (D29,31: F0)............................................... 41
3.2.7
CLS—Cache Line Size Register (D29,31: F0) ..................................... 42
3.2.8
PMLT—Primary Master Latency Timer Register (D29,31: F0)............ 42
3.2.9
HEADTYP—Header Type Register (D29,31: F0)................................. 42
3.2.10 BNUM—Bus Number Register (D29,31: F0)........................................ 43
3.2.11 SMLT—Secondary Master Latency Timer (D29,31: F0) ...................... 43
3.2.12 IOBL_ADR—I/O Base and Limit Address Register D29,31: F04 ........ 44
3.2.13 SECSTS—Secondary Status Register (D29,31: F0)............................ 44
3.2.14 MBL_ADR—Memory Base and Limit Address Register (D29,31: F0) . 46
3.2.15 PMBL_ADR—Prefetchable Memory Base and Limit Address
Register (D29,31: F0) ........................................................................... 46
3.2.16 PREF_MEM_BASE_UPPER—Prefetchable Memory Base
Upper 32 Bit Address Register (D29,31: F0) ........................................ 47
3.2.17 PREF_MEM_LIM_UPPER—Prefetchable Memory Limit
Upper 32 Bit Address Register (D29,31: F0) ........................................ 47
3.2.18 IOBLU16_ADR—I/O Base and Limit Upper 16 Bit Address
Register (D29,31: F0) ........................................................................... 47
3.2.19 CAPP—Capabilities List Pointer Register (D29,31: F0) ....................... 48
3.2.20 INTR—Interrupt Information Register (D29,31: F0).............................. 48
3.2.21 BRIDGE_CNT—Bridge Control Register (D31: F0) ............................. 48
3.2.22 CNF—P64H2 Configuration Register (D29,31: F0).............................. 51
3.2.23 MTT—Multi-Transaction Timer Register (D29,31: F0) ......................... 52
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3.3
STRP—PCI Strap Status Register (D29,31: F0) .................................. 52
PX_CAPID—PCI-X Capabilities Identifier Register (D29,31: F0)........ 53
PX_SSTS—PCI-X Secondary Status Register (D29,31: F0) ............... 53
PX_BSTS—PCI-X Bridge Status Register (D29,31: F0) ...................... 54
PX_USTC—PCI-X Upstream Split Transaction Control
Register (D29,31: F0) ........................................................................... 55
3.2.29 PX_DSTC—PCI-X Downstream Split Transaction Control
Register (D29,31: F0) ........................................................................... 55
3.2.30 RAS_STS—RAS Status Register (D29,31: F0).................................... 56
3.2.31 RAS_DI—RAS Data Integrity Codes Register (D29,31: F0) ................ 59
3.2.32 RAS_PH—RAS PCI Header Register (D29,31: F0) ............................. 59
3.2.33 RAS_PAL—RAS PCI Address Low Register (D29,31: F0) .................. 60
3.2.34 RAS_PAH—RAS PCI Address High Register (D29,31: F0)................. 60
3.2.35 RAS_PDL—RAS PCI Data Low 32 Bits Register (D29,31: F0)........... 60
3.2.36 RAS_PDH—RAS PCI Data High 32 bits Register (D29,31: F0).......... 61
3.2.37 RAS_HH—RAS Hub Interface Header Register (D29,31: F0) ............. 61
3.2.38 RAS_HAL—RAS Hub Interface Address Low 32 Bits
Register (D29,31: F0) ........................................................................... 61
3.2.39 RAS_HAH—RAS Hub Interface Address High 32 Bits
Register (D29,31: F0) ........................................................................... 62
3.2.40 RAS_HP—RAS Hub Interface Prefetch Horizon Register (D29,31: F0)62
3.2.41 RAS_D0—RAS Hub Interface DWord 0 Register (D29,31: F0) .......... 62
3.2.42 RAS_D1—RAS Hub Interface DWord 1 Register (D29,31: F0) .......... 63
3.2.43 RAS_D2—RAS Hub Interface DWord 2 Register (D29,31: F0) .......... 63
3.2.44 RAS_D3—RAS Hub Interface DWord 3 Register (D29,31: F0) .......... 63
3.2.45 ACNF—Additional P64H2 Configuration Register (D29,31: F0).......... 64
3.2.46 PCC—PCI Delay Compensation Control Register (D29,31: F0) ......... 66
3.2.47 HCCR—Hub Interface Command/Control Register (D29,31: F0) ....... 67
3.2.48 Prefetch Control Registers.................................................................... 68
3.2.48.1 PC33—Prefetch Control for 33 MHz
Register (D29,31: F0).......................................................... 68
3.2.48.2 PC66—Prefetch Control for 66 MHz
Register (D29,31: F0).......................................................... 68
3.2.48.3 PC100—Prefetch Control for 100 MHz
Register (D29,31: F0).......................................................... 69
3.2.48.4 PC133—Prefetch Control for 133 MHz
Register (D29,31: F0).......................................................... 69
Hot Plug Controller Registers (Device 31) ........................................................... 70
3.3.1
PCI Configuration Registers ................................................................. 70
3.3.1.1
VID—Vendor ID Register (Device 31)................................. 71
3.3.1.2
DID—Device ID Register (Device 31) ................................. 71
3.3.1.3
PCICMD—PCI Command Register (Device 31) ................. 71
3.3.1.4
PCISTS—PCI Status Register (Device 31)......................... 72
3.3.1.5
RID—Revision ID Register (Device 31) .............................. 72
3.3.1.6
CC—Class Code Register (Device 31) ............................... 73
3.3.1.7
MBAR—Memory Base Register (Device 31) ...................... 73
3.3.1.8
MBARU—Memory Base Address (Upper 32-bits)
Register (Device 31)............................................................ 73
3.3.1.9
SVID—Subsystem Vendor ID Register (Device 31)............ 74
3.3.1.10 SID—Subsystem ID Register (Device 31)........................... 74
3.3.1.11 CAP_PTR—Capabilities Pointer Register (Device 31) ....... 74
3.3.1.12 INTR—Interrupt Information Register (Device 31) .............. 75
3.3.1.13 SID—Slot ID Register (Device 31) ...................................... 75
3.2.24
3.2.25
3.2.26
3.2.27
3.2.28
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3.4
HPFC—Hot Plug Frequency Control Register
(Device 31) .......................................................................... 75
3.3.1.15 MCNF—Miscellaneous Configuration Register
(Device 31) .......................................................................... 76
3.3.1.16 FTR—Features Register (Device 31).................................. 78
3.3.1.17 SSEL—Slot Status Select Register (Device 31) ................. 78
3.3.1.18 SSTS—Slot Status Register (Device 31) ............................ 79
3.3.1.19 SERR—SERR Status Register (Device 31)........................ 80
3.3.1.20 MIDX—Alternate Memory Access Index Port Register
(Device 31) .......................................................................... 80
3.3.1.21 MDTA—Alternate Memory Access Data Port Register
(Device 31) .......................................................................... 81
3.3.1.22 XID—PCI-X Identifiers Register (Device 31)....................... 81
3.3.1.23 XCR—PCI-X Command Register (Device 31) .................... 81
3.3.1.24 XSR—PCI-X Status Register (Device 31)........................... 82
3.3.1.25 ABAR—Alternate Base Register (Device 31)...................... 82
3.3.2
Memory Space Registers ..................................................................... 83
3.3.2.1
GPT—General Purpose Timer Register ............................. 84
3.3.2.2
SE—Slot Enable Register ................................................... 84
3.3.2.3
MCNF—Miscellaneous Configuration Register................... 85
3.3.2.4
LEDC—LED Control Register ............................................. 87
3.3.2.5
HMIC—Hot Plug Interrupt Input and Clear Register ........... 88
3.3.2.6
HMIR—Hot Plug Interrupt Mask Register ........................... 89
3.3.2.7
SIR—Serial Input Register .................................................. 90
3.3.2.8
GPO—General Purpose Output Register ........................... 90
3.3.2.9
HMIN—Hot Plug Non-Interrupt Inputs Register .................. 91
3.3.2.10 SID—Slot ID Register.......................................................... 91
3.3.2.11 SIRE—Switch Interrupt Redirect Enable Register .............. 91
3.3.2.12 SPE—Slot Power Enable Register...................................... 92
3.3.2.13 EMR—Extended Hot Plug Miscellaneous Register............. 93
I/OxAPIC Interrupt Controller Registers ............................................................... 94
3.4.1
PCI Configuration Space Registers (Device 28 and 30)....................... 94
3.4.1.1
VID—Vendor ID Register (D28,30: F0) ............................... 95
3.4.1.2
DID—Device ID Register (D28,30: F0) ............................... 95
3.4.1.3
PCICMD—PCI Device Command Register (D28,30: F0) ... 96
3.4.1.4
PCISTS—PCI Device Status Register (D28,30: F0) ........... 97
3.4.1.5
RID—Revision ID Register (D28,30: F0)............................. 97
3.4.1.6
CC—Class Code Register (D28,30: F0) ............................. 98
3.4.1.7
HDR—Header (D28,30: F0) ................................................ 98
3.4.1.8
MBAR—Memory Base Register (D28,30: F0)..................... 98
3.4.1.9
SS—Subsystem Identifier Register (D28,30: F0)................ 99
3.4.1.10 CAP_PTR—Capabilities Pointer Register (D28,30: F0)...... 99
3.4.1.11 ABAR—Alternate Base Address Register (D28,30: F0)...... 99
3.4.1.12 XID—PCI-X Identifier Register (D28,30: F0)..................... 100
3.4.1.13 XCR—PCI-X Command Register (D28,30: F0) ................ 100
3.4.1.14 XSR—PCI-X Status Register (D28,30: F0) ....................... 100
3.4.2
Direct Memory Space Registers ......................................................... 101
3.4.2.1
IDX—Index Register (D28,30: F0) .................................... 101
3.4.2.2
WND—Window Register (D28,30: F0) ............................. 101
3.4.2.3
PAR—IRQ Pin Assertion Register (D28,30: F0) ............... 102
3.4.2.4
EOI—End of Interrupt Register (D28,30: F0) .................... 102
3.3.1.14
Intel 82870P2 P64H2 Datasheet
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