P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
4 kB/8 kB 3 V byte-erasable flash
Rev. 2.1 — 27 August 2012
Product data sheet
1. General description
The P89LPC9301/931A1 is a single-chip microcontroller, available in low cost packages,
based on a high performance processor architecture that executes instructions in two to
four clocks, six times the rate of standard 80C51 devices. Many system-level functions
have been incorporated into the P89LPC9301/931A1 in order to reduce component count,
board space, and system cost.
2. Features and benefits
2.1 Principal features
4 kB/8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte
pages. Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
256-byte RAM data memory.
Two analog comparators with selectable inputs and reference source.
Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output).
A 23-bit system timer that can also be used as real-time clock consisting of a 7-bit
prescaler and a programmable and readable 16-bit timer.
Enhanced UART with a fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I
2
C-bus
communication port and SPI communication port.
2.4 V to 3.6 V V
DD
operating range. I/O pins are 5 V tolerant (may be pulled up or
driven to 5.5 V).
Enhanced low voltage (brownout) detect allows a graceful system shutdown when
power fails.
28-pin TSSOP and PLCC packages with 23 I/O pins minimum and up to 26 I/O pins
while using on-chip oscillator and reset options.
2.2 Additional features
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
Serial flash In-Circuit Programming (ICP) allows simple production coding with
commercial EPROM programmers. Flash security bits prevent reading of sensitive
application programs.
NXP Semiconductors
P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
Serial flash In-System Programming (ISP) allows coding while the device is mounted
in the end application.
In-Application Programming (IAP) of the flash code memory. This allows changing the
code in a running application.
Watchdog timer with separate on-chip oscillator, nominal 400 kHz, calibrated to
5
%,
requiring no external components. The watchdog prescaler is selectable from
eight values.
High-accuracy internal RC oscillator option, with clock doubler option, allows operation
without external oscillator components. The RC oscillator option is selectable and fine
tunable.
Switching on the fly among internal RC oscillator, watchdog oscillator, external clock
source provides optimal support of minimal power active mode with fast switching to
maximum performance.
Idle and two different power-down reduced power modes. Improved wake-up from
Power-down mode (a LOW interrupt input starts execution). Typical power-down
current is 1
A
(total power-down with voltage comparators disabled).
Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A software reset function is also available.
Configurable on-chip oscillator with frequency range options selected by user
programmed flash configuration bits. Oscillator options support frequencies from
20 kHz to the maximum operating frequency of 18 MHz.
Oscillator fail detect. The watchdog timer has a separate fully on-chip oscillator
allowing it to perform an oscillator fail detect function.
Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
High current sourcing/sinking (20 mA) on eight I/O pins (P0.3 to P0.7, P1.4, P1.6,
P1.7). All other port pins have high sinking capability (20 mA). A maximum limit is
specified for the entire chip.
Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
Only power and ground connections are required to operate the P89LPC9301/931A1
when internal reset option is selected.
Four interrupt priority levels.
Eight keypad interrupt inputs, plus two additional external interrupt inputs.
Schmitt trigger port inputs.
Second data pointer.
Emulation support.
P89LPC9301_931A1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2.1 — 27 August 2012
2 of 66
NXP Semiconductors
P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
3. Ordering information
Table 1.
Ordering information
Package
Name
P89LPC9301FDH
P89LPC931A1FDH
TSSOP28
TSSOP28
Description
plastic thin shrink small outline package; 28
leads; body width 4.4 mm
plastic thin shrink small outline package; 28
leads; body width 4.4 mm
Version
SOT361-1
SOT361-1
Type number
3.1 Ordering options
Table 2.
Ordering options
Flash memory
4 kB
8 kB
Temperature range
40 C
to +85
C
40 C
to +85
C
Frequency
0 MHz to 18 MHz
0 MHz to 18 MHz
Type number
P89LPC9301FDH
P89LPC931A1FDH
P89LPC9301_931A1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2.1 — 27 August 2012
3 of 66
NXP Semiconductors
P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
4. Block diagram
P89LPC9301/931A1
HIGH PERFORMANCE
ACCELERATED 2-CLOCK 80C51 CPU
4 kB/8 kB
CODE FLASH
256-BYTE
DATA RAM
PORT 3
CONFIGURABLE I/Os
PORT 2
CONFIGURABLE I/Os
PORT 1
CONFIGURABLE I/Os
PORT 0
CONFIGURABLE I/Os
internal
bus
UART
REAL-TIME CLOCK/
SYSTEM TIMER
TXD
RXD
P3[1:0]
I
2
C-BUS
SCL
SDA
P2[7:0]
WATCHDOG TIMER
AND OSCILLATOR
TIMER 0
TIMER 1
T0
T1
CMP2
CIN2B
CMP1
CIN1B
P1[7:0]
P0[7:0]
ANALOG
COMPARATORS
CIN2A
CIN1A
SPICLK
MOSI
MISO
SS
KEYPAD
INTERRUPT
SPI
PROGRAMMABLE
OSCILLATOR DIVIDER
XTAL1
CRYSTAL
OR
RESONATOR
XTAL2
CONFIGURABLE
OSCILLATOR
CPU
clock
ON-CHIP RC
OSCILLATOR WITH
CLOCK DOUBLER
POWER MONITOR
(POWER-ON RESET,
BROWNOUT RESET)
002aae447
Fig 1.
Block diagram
P89LPC9301_931A1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2.1 — 27 August 2012
4 of 66
NXP Semiconductors
P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
5. Functional diagram
V
DD
V
SS
KBI0
KBI1
KBI2
KBI3
KBI4
KBI5
KBI6
KBI7
CLKOUT
CMP2
CIN2B
CIN2A
CIN1B
CIN1A
CMPREF
CMP1
T1
XTAL2
PORT 0
PORT 1
TXD
RXD
T0
INT0
INT1
RST
SCL
SDA
P89LPC9301/
931A1
PORT 3
MOSI
MISO
SS
SPICLK
XTAL1
PORT 2
002aae448
Fig 2.
Functional diagram
P89LPC9301_931A1
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 2.1 — 27 August 2012
5 of 66
Embedded System
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