QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
3.3V LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
FEATURES:
DESCRIPTION:
QS5LV919
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3.3V operation
JEDEC compatible LVTTL level outputs
Clock inputs are 5V tolerant
< 300ps output skew, Q
0
–Q
4
2xQ output, Q outputs,
Q
output, Q/2 output
Outputs 3-state and reset while OE/RST low
PLL disable feature for low frequency testing
Internal loop filter RC network
Functional equivalent to MC88LV915, IDT74FCT388915
Positive or negative edge synchronization (PE)
Balanced drive outputs ±24mA
160MHz maximum frequency (2xQ output)
Available in QSOP and PLCC packages
The QS5LV919 Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to one of two reference clock inputs.
Eight outputs are available: 2xQ, Q
0
-Q
4
, Q
5
, Q/2. Careful layout and
design ensure < 300 ps skew between the Q
0
-Q
4
, and Q/2 outputs.
The QS5LV919 includes an internal RC filter which provides excellent
jitter characteristics and eliminates the need for external components.
Various combinations of feedback and a divide-by-2 in the VCO path
allow applications to be customized for linear VCO operation over a
wide range of input SYNC frequencies. The PLL can also be disabled
by the PLL_EN signal to allow low frequency or DC testing. The LOCK
output asserts to indicate when phase lock has been achieved. The
QS5LV919 is designed for use in high-performance workstations, multi-
board computers, networking hardware, and mainframe systems. Sev-
eral can be used in parallel or scattered throughout a system for guar-
anteed low skew, system-wide clock distribution networks.
For more information on PLL clock driver products, see Application
Note AN-227.
FUNCTIONAL BLOCK DIAGRAM
REF_SEL
LO CK
SYNC
0
SYNC
1
O E/RST
0
0
1
PH A SE
DETECTO R
LOO P
FILTER
1
PE
FEEDBACK
PLL_EN
FREQ _SEL
VCO
1
/2
0
R
D
R
D
R
D
R
D
R
D
R
D
R
D
Q
Q
Q
Q
Q
Q
Q
Q
Q /
2
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
2xQ
INDUSTRIAL TEMPERATURE RANGE
1
c
2001
Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
JULY 2001
DSC-5820/3
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE/RST
GND
Q
5
V
DD
OE/RST
FEEDBACK
REF_SEL
SYNC
0
AV
DD
PE
AGND
SYNC
1
FREQ_SEL
GND
Q
0
2
3
4
5
6
7
8
9
10
11
12
13
14
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
2xQ
Q/2
GND
Q
3
V
DD
Q
2
GND
LOCK
PLL_EN
GND
Q
1
V
DD
AGND
SYNC
1
10
11
FEEDBACK
REF_SEL
SYNC
0
AV
DD
PE
5
6
7
8
9
4
3
2
1
28
27
26
25
24
23
22
21
20
19
Q/2
GND
Q
3
V
DD
Q
2
GND
LOCK
12
FREQ_SEL
13
GND
14
Q
0
15
V
DD
16
Q
1
17
GND
18
PLL_EN
QSOP
TOP VIEW
PLCC
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
DC Input Voltage V
IN
Maximum Power
T
STG
QSOP
Dissipation (T
A
= 85°C) PLCC
Storage Temperature Range
Max.
–0.5 to +7
–0.5 to +5.5
655
770
–65 to +150
Unit
V
V
mW
mW
°C
V
DD
, AV
DD
Supply Voltage to Ground
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= 25
°
C, f = 1MHz, V
IN
= 0V)
QSOP
Parameter
C
IN
Typ.
3
Max.
4
Typ.
4
PLCC
Max.
6
Unit
pF
2
2xQ
V
DD
Q
5
Q
4
V
DD
GND
1
28
Q
4
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name
SYNC
0
SYNC
1
REF_SEL
FREQ_SEL
FEEDBACK
Q
0
-Q
4
Q
5
2xQ
Q/2
LOCK
OE/RST
PLL_EN
PE
V
DD
AV
DD
GND
AGND
I/O
I
I
I
I
I
O
O
O
O
O
I
I
I
—
—
—
—
Description
Reference clock input
Reference clock input
Reference clock select. When 1, selects SYNC
1
. When 0, selects SYNC
0
.
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.
PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different
output frequency relationships. See the Frequency Selection Table for more information.
Clock outputs
Clock output. Matched in frequency, but inverted with respect to Q.
Clock output. Matched in phase, but frequency is double the Q frequency.
Clock output. Matched in phase, but frequency is half the Q frequency.
PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be
synchronized to the inputs.
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When
1, outputs are enabled.
PLL enable. Enables and disables the PLL. Useful for testing purposes.
When
PE
is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with
the negative edge of SYNC.
Power supply for output buffers.
Power supply for phase lock loop and other internal circuitries.
Ground supply for output buffers.
Ground supply for phase lock loop and other internal circuitries.
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= –40°C to +85°C, AV
DD
/ V
DD
= 3.3V ± 0.3V
Symbol
F
MAX_2XQ
F
MAX_Q
F
MAX_Q/2
F
MIN_2XQ
F
MIN_Q
F
MIN_Q/2
Description
Max Frequency, 2xQ
Max Frequency, Q
0
- Q
4
, Q
5
Max Frequency, Q/2
Min Frequency, 2xQ
Min Frequency, Q
0
- Q
4
, Q
5
Min Frequency, Q/2
– 55
55
27.5
13.75
20
10
5
– 70
70
35
17.5
20
10
5
– 100
100
50
25
20
10
5
– 133
133
66.5
33.25
20
10
5
– 160
160
80
40
20
10
5
Units
MHz
MHz
MHz
MHz
MHz
MHz
3
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
FREQUENCY SELECTION TABLE
SYNC (MHz)
Output Used for
FREQ_SEL
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
Feedback
Q/2
Q
0
-Q
4
Q
5
2xQ
(3)
Q/2
Q
0
-Q
4
Q
5
2xQ
(allowable range)
(1)
Min.
F
MIN_Q/2
F
MIN_Q
F
MIN_Q
F
MIN_2XQ
F
MIN_Q/2
/2
F
MIN_Q
/2
F
MIN_Q
/2
F
MIN_2XQ
/2
Max
F
MAX _Q/2
F
MAX _Q
F
MAX _Q
100
F
MAX _Q/2
/2
F
MAX _Q
/2
F
MAX _Q
/2
F
MAX _2XQ
/2
Q/
2
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
SYNC
SYNC / 2
– SYNC / 2
SYNC / 4
Output Frequency Relationships
(2)
Q
5
– SYNC X 2
– SYNC
SYNC
– SYNC / 2
– SYNC X 2
– SYNC
SYNC
– SYNC / 2
Q
0
- Q
4
SYNC X 2
SYNC
– SYNC
SYNC / 2
SYNC X 2
SYNC
– SYNC
SYNC / 2
2XQ
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
SYNC X 4
SYNC X 2
– SYNC X 2
SYNC
NOTES:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 20MHz to F
MAX_2
X
Q
. Operation with Sync inputs outside
specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output frequencies.
2. The lock output pin (LOCK) may not indicate reliably for VCO frequencies below 30MHz.
3. The 2xQ is limited to a maximum frequency (F
MAX_2XQ
) of 100MHz only when used as a feedback.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified
Industrial: T
A
= -40°C to +85°C, AV
DD
/V
DD
= 3.3V ± 0.3V
Symbol
V
IH
V
IL
V
OH
V
OL
V
H
I
OZ
I
IN
I
PD
Parameter
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Hysteresis
Output Leakage Current
Input Leakage Current
Input Pull-Down Current (PE)
Conditions
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
I
OH
=
−
24mA
I
OH
=
−
100µA
V
DD
= Min., I
OL
= 100µA
—
V
OUT
= V
DD
or GND, V
DD
= Max.
AV
DD
= Max., V
IN
= AV
DD
or GND
AV
DD
= Max., V
IN
= AV
DD
Min.
2
—
V
DD
– 0.6
V
DD
– 0.2
—
—
—
—
—
—
Typ.
—
—
—
—
—
—
100
—
—
—
Max.
—
0.8
—
—
0.45
0.2
—
±5
±5
± 100
mV
µA
µA
µA
V
Unit
V
V
V
V
DD
= Min., I
OL
= 24mA
POWER SUPPLY CHARACTERISTICS
Symbol
I
DDQ
∆I
DD
I
DDD
NOTE:
1. Relative to the frequency of Q outputs.
Parameter
Quiescent Power Supply Current
Power Supply Current per Input HIGH
Dynamic Power Supply Current
(1)
Test Conditions
V
DD
= Max., OE/RST = LOW,
SYNC = LOW, All outputs unloaded
V
DD
= Max., V
IN
= 3V
V
DD
= Max., C
L
= 0pF
Typ.
Max.
1
Unit
mA
µA
mA/MHz
1
0.2
30
0.4
4
QS5LV919
3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
INDUSTRIAL TEMPERATURE RANGE
INPUT TIMING REQUIREMENTS
Symbol
t
R
, t
F
F
I
t
PWC
D
H
Description
(1)
Maximum input rise and fall times, 0.8V to 2V
Input Clock Frequency, SYNC
0
, SYNC
1
(1)
Input clock pulse, HIGH or LOW
(2)
Input duty cycle, SYNC
0
, SYNC
1
(2)
Min.
—
2.5
2
25
Max.
3
100
—
75
Unit
ns
MHz
ns
%
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with different FEEDBACK and
FREQ_SEL combinations.
2. Where pulse witdh implied by D
H
is less than t
WPC
limit, t
WPC
limit applies
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
t
SKR
t
SKF
t
SKALL
t
PW
t
PW
t
J
t
PD
t
LOCK
t
PZH
t
PZL
t
PHZ
t
PLZ
t
R,
t
F
Output Rise/Fall Times, 0.8V
∼
2V
0.3
2
ns
Output Disable Time, OE/RST HIGH to LOW
(3)
0
14
ns
Parameter
(1)
Output Skew Between Rising Edges, Q
0
-Q
4
(and Q/
2
if
PE
= LOW)
(2)
Output Skew Between Falling Edges, Q
0
-Q
4
(and Q/
2
if
PE
= HIGH)
(2)
Output Skew, All Outputs
(2, 5)
Pulse Width, 2xQ output, >40MHz
Pulse Width, Q
0
-Q
4
, Q
5,
Q/2 outputs, 80MHz
Cycle-to-Cycle Jitter
(4)
SYNC Input to Feedback Delay
(6)
SYNC to Phase Lock
Output Enable Time, OE/RST LOW to HIGH
(3)
Min.
—
—
—
T
CY
/2
−
0.4
T
CY
/2
−
0.4
Max.
300
300
500
T
CY
/2 + 0.4
T
CY
/2 + 0.4
0.15
0
10
14
Unit
ps
ps
ps
ns
ns
ns
ps
ms
ns
−
0.15
−
500
—
0
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input frequencies.
5. Skew measured at selected synchronization edge.
6. t
PD
measured at device inputs at 0.5V
DD
, Q output at 80MHz.
5
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