Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
See Figure 3 and Figure 4.
3
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
4
SCLK active edge is falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY
returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
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