Am45DL3208G
Data Sheet
September 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
26460
Revision
B
Amendment
+1
Issue Date
March 12, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
PRELIMINARY
Am45DL3208G
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash
Memory and 8 Mbit (1 M x 8-Bit/512 K x 16-Bit) Pseudo Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
■
Power supply voltage of 2.7 to 3.3 volt
■
High performance
— Access time as fast as 70 ns
■
20 year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
■
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
■
Package
— 73-Ball FBGA
■
Operating Temperature
— –40°C to +85°C
■
Supports Common Flash Memory Interface (CFI)
■
Program/Erase Suspend/Erase Resume
— Suspends program/erase operations to allow
programming/erasing in same bank
Flash Memory Features
ARCHITECTURAL ADVANTAGES
■
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in another bank.
— Zero latency between read and write operations
■
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
program command sequences
■
Flexible Bank™ architecture
— Read may occur in any of the three banks not being written
or erased.
— Four banks may be grouped by customer to achieve desired
bank divisions.
HARDWARE FEATURES
■
Any combination of sectors can be erased
■
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase cycle
completion
■
Manufactured on 0.17 µm process technology
■
SecSi™ (Secured Silicon) Sector: Extra 256 Byte sector
—
Factory locked and identifiable:
16 bytes available for
secure, random factory Electronic Serial Number; verifiable
as factory locked through autoselect function. ExpressFlash
option allows entire sector to be available for
factory-secured data
—
Customer lockable:
Sector is one-time programmable. Once
sector is locked, data cannot be changed.
■
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state machine to
the read mode
■
WP#/ACC input pin
— Write protect (WP#) function protects sectors 0 and 1
(bottom boot) or 69 and 70 (top boot), regardless of sector
protect status
— Acceleration (ACC) function accelerates program timing
■
Zero Power Operation
— Sophisticated power management circuits reduce power
consumed during inactive periods to nearly zero.
■
Sector protection
— Hardware method of locking a sector, either in-system or
using programming equipment, to prevent any program or
erase operation within that sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
■
Top or bottom boot sectors
■
Compatible with JEDEC standards
— Pinout and software compatible with single-power-supply
flash standard
PERFORMANCE CHARACTERISTICS
■
High performance
— Access time as fast as 70 ns
— Program time: 4 µs/word typical utilizing Accelerate function
Pseudo SRAM Features
■
Power dissipation
— Operating: 30 mA maximum
— Standby: 100 µA maximum
■
Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■
CE1s# and CE2s Chip Select
■
Power down features using CE1s# and CE2s
■
Data retention supply voltage: 2.7 to 3.3 volt
■
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
■
Minimum 1 million write cycles guaranteed per sector
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
26460
Rev:
B
Amendment/+1
Issue Date:
March 12, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
Am29DL320G Features
The Am29DL320G is a 32 megabit, 3.0 volt-only flash
memory device, organized as 2,097,152 words of 16
bits each or 4,194,304 bytes of 8 bits each. Word
mode data appears on DQ15–DQ0; byte mode data
appears on DQ7–DQ0. The device is designed to be
programmed in-system with the standard 3.0 volt V
CC
supply, and can also be programmed in standard
EPROM programmers.
The device is available with an access time of 70 or 85
ns and is offered in a 73-ball FBGA package. Standard
control pins—chip enable (CE#f), write enable (WE#),
and output enable (OE#)—control normal read and
write operations, and avoid bus contention issues.
The device requires only a
single 3.0 volt power sup-
ply
for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as a one-time programmable area.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
is a n a dva n t a g e co m p a r e d t o sy st e m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and soft-
ware integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into
four banks,
two 4 Mb banks with small and
large sectors, and two 12 Mb banks of large sectors
only. Sector addresses are fixed, system software can
be used to form user-defined bank groups.
During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device can im-
prove overall system performance by allowing a host
system to program or erase in one bank, then
immediately and simultaneously read from the other
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.
The Am29DL320G can be organized as both a top
and bottom boot sector configuration.
Bank
Bank 1
Bank 2
Bank 3
Bank 4
Megabits
4 Mb
12 Mb
12 Mb
4 Mb
Sector Sizes
Eight 8 Kbyte/4 Kword,
Seven 64 Kbyte/32 Kword
Forty-eight 64 Kbyte/32 Kword
Forty-eight 64 Kbyte/32 Kword
Sixteen 64 Kbyte/32 Kword
The
SecSi™ (Secured Silicon) Sector
is an extra
256 byte sector capable of being permanently locked
by AMD or customers. The
SecSi Indicator Bit
(DQ7)
is permanently set to a 1 if the part is
factory locked,
and set to a 0 if
customer lockable.
This way, cus-
tomer lockable parts can never be used to replace a
factory locked part.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
2
Am45DL3208G
March 12, 2004
P R E L I M I N A R Y
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5
MCP Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . 5
Flash memory Block Diagram . . . . . . . . . . . . . . . 6
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7
Special Package Handling Instructions .................................... 7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2. Device Bus Operations—Flash Word Mode, CIOf = V
IH
;
PSRAM Byte Mode, CIOs = V
SS
....................................................11
Table 3. Device Bus Operations—Flash Byte Mode, CIOf = V
SS
;
PSRAM Word Mode, CIOs = V
CC
..................................................12
Table 4. Device Bus Operations—Flash Byte Mode, CIOf = V
IL
;
PSRAM Byte Mode, CIOs = V
SS
....................................................13
Figure 6. Data# Polling Algorithm .................................................. 33
RY/BY#: Ready/Busy# ............................................................ 34
DQ6: Toggle Bit I .................................................................... 34
Figure 7. Toggle Bit Algorithm........................................................ 34
DQ2: Toggle Bit II ................................................................... 35
Reading Toggle Bits DQ6/DQ2 ............................................... 35
DQ5: Exceeded Timing Limits ................................................ 35
DQ3: Sector Erase Timer ....................................................... 35
Table 17. Write Operation Status ................................................... 36
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 37
Figure 8. Maximum Negative Overshoot Waveform ...................... 37
Figure 9. Maximum Positive Overshoot Waveform........................ 37
Flash DC Characteristics . . . . . . . . . . . . . . . . . . 38
CMOS Compatible .................................................................. 38
Figure 10. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents) ............................................................. 39
Figure 11. Typical I
CC1
vs. Frequency............................................ 39
Word/Byte Configuration ........................................................ 13
Requirements for Reading Array Data ................................... 13
Writing Commands/Command Sequences ............................ 14
Accelerated Program Operation .......................................... 14
Autoselect Functions ........................................................... 14
Simultaneous Read/Write Operations with Zero Latency ....... 14
Standby Mode ........................................................................ 14
Automatic Sleep Mode ........................................................... 15
RESET#: Hardware Reset Pin ............................................... 15
Output Disable Mode .............................................................. 15
Table 5. Top Boot Sector Addresses .............................................15
Table 7. Bottom Boot Sector Addresses .........................................17
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 12. Test Setup.................................................................... 41
Figure 13. Input Waveforms and Measurement Levels ................. 41
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 42
Pseudo SRAM CE#s Timing ................................................... 42
Figure 14. Timing Diagram for Alternating
Between Pseudo SRAM and Flash................................................ 42
Read-Only Operations ........................................................... 43
Figure 15. Read Operation Timings ............................................... 43
Sector/Sector Block Protection and Unprotection .................. 19
Table 9. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................19
Table 10. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection .............................................................19
Hardware Reset (RESET#) .................................................... 44
Figure 16. Reset Timings ............................................................... 44
Word/Byte Configuration (CIOf) .............................................. 45
Figure 17. CIOf Timings for Read Operations................................ 45
Figure 18. CIOf Timings for Write Operations................................ 45
Write Protect (WP#) ................................................................ 20
Temporary Sector Unprotect .................................................. 20
Figure 1. Temporary Sector Unprotect Operation........................... 20
Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 21
Flash Erase and Program Operations .................................... 46
Figure 19. Program Operation Timings..........................................
Figure 20. Accelerated Program Timing Diagram..........................
Figure 21. Chip/Sector Erase Operation Timings ..........................
Figure 22. Back-to-back Read/Write Cycle Timings ......................
Figure 23. Data# Polling Timings (During Embedded Algorithms).
Figure 24. Toggle Bit Timings (During Embedded Algorithms)......
Figure 25. DQ2 vs. DQ6.................................................................
47
47
48
49
49
50
50
SecSi™ (Secured Silicon) Sector
Flash Memory Region ............................................................ 22
Figure 3. SecSi Sector Protect Verify.............................................. 23
Hardware Data Protection ...................................................... 23
Low V
CC
Write Inhibit ........................................................... 23
Write Pulse “Glitch” Protection ............................................ 23
Logical Inhibit ...................................................................... 23
Power-Up Write Inhibit ......................................................... 23
Flash Command Definitions . . . . . . . . . . . . . . . . 27
Reading Array Data ................................................................ 27
Reset Command ..................................................................... 27
Autoselect Command Sequence ............................................ 27
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .............................................................. 27
Byte/Word Program Command Sequence ............................. 28
Unlock Bypass Command Sequence .................................. 28
Figure 4. Program Operation .......................................................... 29
Temporary Sector Unprotect .................................................. 51
Figure 26. Temporary Sector Unprotect Timing Diagram .............. 51
Figure 27. Sector/Sector Block Protect and
Unprotect Timing Diagram ............................................................. 52
Alternate CE#f Controlled Erase and Program Operations .... 53
Figure 28. Flash Alternate CE#f Controlled Write (Erase/Program)
Operation Timings.......................................................................... 54
Power Up Time ....................................................................... 55
Read Cycle ............................................................................. 55
Figure 29. Pseudo SRAM Read Cycle—Address Controlled......... 55
Read Cycle ............................................................................. 56
Figure 30. Pseudo SRAM Read Cycle........................................... 56
Write Cycle ............................................................................. 57
Figure 31. Pseudo SRAM Write Cycle—WE# Control ................... 57
Figure 32. Pseudo SRAM Write Cycle—CE1#s Control ................ 58
Figure 33. Pseudo SRAM Write Cycle—
UB#s and LB#s Control.................................................................. 59
Chip Erase Command Sequence ........................................... 29
Sector Erase Command Sequence ........................................ 29
Erase Suspend/Erase Resume Commands ........................... 30
Figure 5. Erase Operation............................................................... 30
Flash Write Operation Status . . . . . . . . . . . . . . . . 33
DQ7: Data# Polling ................................................................. 33
March 12, 2004
Flash Erase And Programming Performance . . 60
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 60
Package Pin Capacitance. . . . . . . . . . . . . . . . . . . 60
Am45DL3208G
3
FPGA/CPLD
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