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SSM3K02T

Description
High Speed Switching Applications
CategoryDiscrete semiconductor    The transistor   
File Size217KB,5 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
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SSM3K02T Overview

High Speed Switching Applications

SSM3K02T Parametric

Parameter NameAttribute value
MakerToshiba Semiconductor
package instructionSMALL OUTLINE, R-PDSO-G3
Contacts3
Reach Compliance Codeunknow
ECCN codeEAR99
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage30 V
Maximum drain current (Abs) (ID)2.5 A
Maximum drain current (ID)2.5 A
Maximum drain-source on-resistance0.25 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
JESD-30 codeR-PDSO-G3
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)1.25 W
Certification statusNot Qualified
surface mountYES
Terminal surfaceTIN LEAD
Terminal formGULL WING
Terminal locationDUAL
transistor applicationsSWITCHING
Transistor component materialsSILICON
Base Number Matches1
SSM3K02T
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type
SSM3K02T
High Speed Switching Applications
Small package
Low on resistance: R
on
= 200 mΩ (max) (V
GS
= 4 V)
: R
on
= 250 mΩ (max) (V
GS
= 2.5 V)
Low gate threshold voltage: V
th
= 0.6~1.1 V (V
DS
= 3 V, I
D
= 0.1 mA)
Unit: mm
Absolute Maximum Ratings
(Ta
=
25°C)
Characteristics
Drain-source voltage
Gate-source voltage
Drain current
DC
Pulse
Symbol
V
DS
V
GSS
I
D
I
DP
P
D
(Note 1)
T
ch
T
stg
Rating
30
±10
2.5
5.0
1250
150
−55~150
Unit
V
V
A
mW
°C
°C
Drain power dissipation (Ta
=
25°C)
Channel temperature
Storage temperature range
JEDEC
JEITA
Note:
Using continuously under heavy loads (e.g. the application of
TOSHIBA
2-3S1A
high temperature/current/voltage and the significant change in
Weight: 0.01 g (typ.)
temperature, etc.) may cause this product to decrease in the
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the absolute maximum ratings.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 1: Mounted on FR4 board
2
(25.4 mm
×
25.4 mm
×
1.6 t, Cu pad: 645 mm , t
=
10 s)
Note 2: The pulse width limited by max channel temperature.
Marking
3
Equivalent Circuit
3
KU
1
2
1
2
Handling Precaution
When handling individual devices (which are not yet mounted on a circuit board), be sure that the environment
is protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other
objects that come into direct contact with devices should be made of anti-static materials.
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