TC74HC165AP/AF/AFN
TOSHIBA CMOS Digital Integrated Circuit
Silicon Monolithic
TC74HC165AP,TC74HC165AF,TC74HC165AFN
8-Bit Shift Register (P-IN, S-OUT)
The TC74HC165A is a high speed CMOS 8-BIT
PARALLEL/SERIAL-IN, SERIAL-OUT SHIFT REGISTER
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent
LSTTL while maintaining the CMOS low power dissipation.
It consists of parallel-in or serial-in, serial-out 8-bit shift
register with a gated clock inputs. When the SHIFT/
LOAD
input is held high, the serial data input is enabled and the eight
frip-frops perform serial shifting with each clock pulse.
When the SHIFT/
LOAD
input is held low, the parallel data is
loaded asynchronously into the register at positive going
transition of the clock pulse.
The CK-INH input should be shifted high only when the CK
input is held high.
All inputs are equipped with protection circuits against static
discharge or transient excess voltage.
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74HC165AP
TC74HC165AF
Features
•
•
•
•
•
•
•
•
High speed: f
max
= 56 MHz (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 4
μA
(max) at Ta = 25°C
High noise immunity: V
NIH
= V
NIL
= 28% V
CC
(min)
Output drive capability: 10 LSTTL loads
Symmetrical output impedance: |I
OH
| = I
OL
= 4 mA (min)
Balanced propagation delays: t
pLH
∼
t
pHL
−
Wide operating voltage range: V
CC
(opr) = 2 to 6 V
Pin and function compatible with 74LS165
TC74HC165AFN
Pin Assignment
Weight
DIP16-P-300-2.54A
SOP16-P-300-1.27A
SOL16-P-150-1.27
: 1.00 g (typ.)
: 0.18 g (typ.)
: 0.13 g (typ.)
1
2007-10-01
TC74HC165AP/AF/AFN
System Diagram
Absolute Maximum Ratings (Note 1)
Characteristics
Supply voltage range
DC input voltage
DC output voltage
Input diode current
Output diode current
DC output current
DC V
CC
/ground current
Power dissipation
Storage temperature
Symbol
V
CC
V
IN
V
OUT
I
IK
I
OK
I
OUT
I
CC
P
D
T
stg
Rating
−
0.5 to 7
−
0.5 to V
CC
+
0.5
−
0.5 to V
CC
+
0.5
±
20
±
20
±
25
±
50
Unit
V
V
V
mA
mA
mA
mA
mW
°C
500 (DIP) (Note 2)/180 (SOP)
−
65 to 150
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta
= −40
to 65°C. From Ta
=
65 to 85°C a derating factor of
−10
mW/°C shall be
applied until 300 mW.
4
2007-10-01
FPGA/CPLD
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