FemtoClock
®
Crystal-to-LVDS
Clock Generator
General Description
The ICS844201-45 is a PCI Express
TM
Clock Generator. The
ICS844201-45 can synthesize 100MHz or 125MHz reference clock
frequencies with a 25MHz crystal. The ICS844201-45 has excellent
phase jitter performance and is packaged in a small 8-pin TSSOP,
making it ideal for use in systems with limited board space.
ICS844201-45
DATASHEET
Features
•
•
•
•
•
•
•
•
•
One differential LVDS output
Crystal oscillator interface designed for 18pF,
25MHz parallel resonant crystal
VCO range: 490MHz – 680MHz
RMS phase jitter at 100MHz (12kHz – 20MHz): 0.792ps (typical)
RMS phase jitter at 125MHz (12kHz – 20MHz): 0.773ps (typical)
Full 3.3V output supply mode
PCI Express (2.5Gb/s) and Gen 2 (5Gb/S) jitter compliant
0°C to 70°C ambient operating temperature
Lead-free (RoHS 6) packaging
Frequency Table
Inputs
Crystal Frequency (MHz)
25
25
M
20
20
FSEL
1
0
N
4
5
Multiplication Value M/N
5
4
Output Frequency Range
(MHz)
125 (default)
100
Block Diagram
XTAL_IN
Pin Assignment
Phase
Detector
VCO
490MHz - 680MHz
OSC
XTAL_OUT
N = ÷5
÷4
(default)
Q
nQ
GND
XTAL_OUT
XTAL_IN
FSEL
1
2
3
4
8
7
6
5
Q
nQ
V
DD
nc
M = ÷20
(fixed)
FSEL
Pullup
ICS844201-45
8 Lead TSSOP
4.40mm x 3.0mm x 0.925mmpackage body
G Package
Top View
ICS844201BG-45
REVISION A OCTOBER 1, 2013
1
©2013 Integrated Device Technology, Inc.
ICS844201-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1
2,
3
4
5
6
7, 8
Name
GND
XTAL_OUT
XTAL_IN
FSEL
nc
V
DD
nQ, Q
Power
Input
Input
Unused
Power
Output
Pullup
Type
Description
Power supply ground.
Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output.
Frequency select pin. LVCMOS/LVTTL interface levels.
No connect.
Power supply pin.
Differential output pair. LVDS interface levels.
NOTE:
Pullup
refers to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
Parameter
Input Capacitance
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
Maximum
Units
pF
k
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics
or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
XTAL_IN
Other Inputs
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
0V to V
DD
-0.5V to V
DD
+ 0.5V
10mA
15mA
129.5C/W (0 mps)
-65C to 150C
ICS844201BG-45
REVISION A OCTOBER 1, 2013
2
©2013 Integrated Device Technology, Inc.
ICS844201-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= 0°C to 70°C
Symbol
V
DD
I
DD
Parameter
Positive Supply Voltage
Power Supply Current
Test Conditions
Minimum
2.97
Typical
3.3
Maximum
3.63
95
Units
V
mA
Table 3B. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= 0°C to 70°C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
V
DD
= V
IN
= 3.63V
V
DD
= 3.63V, V
IN
= 0V
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
DD
+ 0.3
0.8
5
Units
V
V
µA
µA
Table 3C. LVDS DC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= 0°C to 70°C
Symbol
V
OD
V
OD
V
DIFF_OUT
V
OS
V
OS
Parameter
Differential Output Voltage
V
OD
Magnitude Change
Peak-to-Peak Differential
Output Voltage
Offset Voltage
V
OS
Magnitude Change
494
1.3
Test Conditions
Minimum
247
Typical
Maximum
454
50
908
1.63
50
Units
mV
mV
mV
V
mV
Table 4. Crystal Characteristics
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
24.5
Test Conditions
Minimum
Typical
Fundamental
25
34
50
7
MHz
pF
Maximum
Units
ICS844201BG-45
REVISION A OCTOBER 1, 2013
3
©2013 Integrated Device Technology, Inc.
ICS844201-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
AC Electrical Characteristics
Table 5. AC Characteristics,
V
DD
= 3.3V ± 10%, T
A
= 0°C to 70°C
Symbol
f
OUT
Parameter
Output Frequency
125MHz, Integration Range:
12kHz – 20MHz
100MHz, Integration Range:
12kHz – 20MHz
125MHz, (1.2MHz – 21.9MHz
25MHz crystal input
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
100MHz, (1.2MHz – 21.9MHz)
25MHz crystal input Evaluation
Band: 0Hz - Nyquist
(clock frequency/2)
125MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
100MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
High Band: 1.5MHz - Nyquist
(clock frequency/2)
125MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
Low Band: 10kHz - 1.5MHz
100MHz, (1.2MHz – 21.9MHz)
25MHz crystal input
Low Band: 10kHz - 1.5MHz
20% to 80%
f
OUT
= 125MHz
f
OUT
= 100MHz
250
48
46
Test Conditions
Minimum
Typical
125
100
0.773
0.792
Maximum
Units
MHz
MHz
ps
ps
tjit(Ø)
RMS Phase Jitter,
Random; NOTE 1
12.51
ps
t
j
Phase Jitter
Peak-to-Peak;
NOTE 2
13.48
ps
1.13
ps
t
REFCLK_HF_RMS
Phase Jitter RMS;
NOTE 3
1.25
ps
0.32
ps
t
REFCLK_LF_RMS
Phase Jitter RMS;
NOTE 3
0.33
450
52
54
ps
ps
%
%
t
R
/ t
F
odc
Output Rise/Fall Time
Output Duty Cycle
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized using a 25MHz crystal.
NOTE 1: Refer to Phase Noise Plots.
NOTE 2: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10
6
clock periods. See IDT Application Note
PCI Express Reference Clock Requirements
and also
the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
NOTE 3: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t
REFCLK_HF_RMS
(High Band) and 3.0 ps RMS for t
REFCLK_LF_RMS
(Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also
the PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.
ICS844201BG-45
REVISION A OCTOBER 1, 2013
4
©2013 Integrated Device Technology, Inc.
ICS844201-45 Data Sheet
FEMTOCLOCK
®
CRYSTAL-TO-LVDS CLOCK GENERATOR
Typical Phase Noise at 100MHz
100MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.792ps (typical)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
Typical Phase Noise at 125MHz
125MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.773ps (typical)
Noise Power (dBc/Hz)
Offset Frequency (Hz)
ICS844201BG-45
REVISION A OCTOBER 1, 2013
5
©2013 Integrated Device Technology, Inc.
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