T6LE2
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6LE2
Gate Driver for TFT LCD Panels
The T6LE2 is a 300
/
263
/
256-channel output gate driver for
TFT LCD panels.
T6LE2
Unit: mm
User Area Pitch
IN
OUT
Features
•
LCD drive output pins
•
LCD drive voltage
•
Data transfer method
•
Operating temperature
•
Package
: Switchable 300
/
263
/
256 pins
: max 43.5 V
: Bidirectional shift register
:
−20
to 75°C
: COF
Please contact Toshiba or a distributor for
the latest COF specification and product
line-up.
COF (Chip On Film)
Application
Module for PC monitors, LCDs for TV and Module for amusement
1
2006-09-20
T6LE2
Block Diagram
DO/I
DI/O
CPVL/R
U/D
MODE1
MODE2
Input circuit unit
Shift register
OE
L/R
Control circuit unit
XDON
V
GG
Output circuit unit
V
EE
V
DD
V
SS
G1
G2
G3
G298 G299 G300
2
2006-09-20
T6LE2
Pin Assignment
G300
G299
G298
327
326
325
T6LE2
(chip top view)
G3
G2
G1
30
29
28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
V
GG
V
EE
V
DD
V
SS
V
DD
DO/I
(V
SS
)
MODE2
(V
DD
)
OE
R
CPVR
V
SS
XDON
(V
DD
)
U/D
(V
SS
)
CPVL
OE
L
(V
SS
)
(V
DD
)
MODE1
(V
SS
)
DI/O
V
SS
V
DD
V
EE
V
GG
The above diagram shows the device’s pin configuration only and does not necessarily correspond to the pad
layout on the chip. Please contact Toshiba or our distributors for the latest COF specification.
3
2006-09-20
T6LE2
Pin Function
Pin Name
I/O
Function
Vertical shift clock, output enable input / output select pin
These pins are used to input and output shift data. These pins are switched between input and
output by setting the U/D pin as shown below.
U/D
DI/O
DO/I
H
I/O
L
DI/O
Input
Output
DO/I
Output
Input
•
When set for input
This pin is used to feed data into the shift registers at the first stage of the LCD driver. The data is
latched into the shift registers at the rising edge of CPVL/R.
•
When set for output
When two or more T6LE2 are cascaded, this pin outputs the data to be fed into the next stage.
This data changes state synchronously with the falling edge of CPVL/R.
Transfer direction select / vertical shift clock, output enable input / output select pin
This pin specifies the direction in which data is transferred through the shift registers.
The shift register data is shifted synchronously with the rising edge of CPV as follows:
When U/D is high, data is shifted in the direction
U/D
=
“H”: G1
→
G2
→
G3
→
G4
→
···
→
G300
When U / D is low, the direction is reversed to give
U/D
=
“L”: G300
→
G299
→
G298
→
G297
→
···
→
G1
This pin is used to perform input / output settings for CPVL, CPVR,
OE
L,
OE
R.
U/DL
U/DR
I/O
U/D
L
Input
CPVR
OE
R
Output
CPVL
OE
L
H
CPVL
OE
L
CPVR
OE
R
The voltage applied to this pin must be a DC-level voltage that is either high (V
DD
) or low (V
SS
).
Vertical shift clock
•
When set for input:
This is the shift clock for the shift registers. Data is shifted through the shift registers
synchronously with the rising edge of CPVL/R.
•
When set for output:
The signal input to CPVL/R is output to CPVR/L asynchronous to other signals.
These pins are switched between input and output by setting the U/D pin as below.
U/D
H
L
CPVL
Input
Output
CPVR
Output
Input
CPVL
CPVR
I/O
OE
L
OE
R
I/O
Output enable pin
When set for input:
These signals control the data appearing at the LCD panel drive pins (G1 through G300).
OE
L/R doesn’t synchronize with the CPVL/R.
When
OE
L/R is low : outputs shift data and data contents.
When
OE
L/R is high : controls the LCD panel drive output to V
EE
level.
When set for output:
The signal input to
OE
L/R is output to
OE
R/L.
These pins are switched between input and output by setting the U/D pin as below.
U/D
H
L
OE
L
OE
R
Input
Output
Output
Input
4
2006-09-20
T6LE2
Pin Name
I/O
Function
Output channels select pins
This signal selects 300 / 263
/
256-pin mode for the LCD panel driver.
MODE1
MODE1
MODE2
I
H
H
L
L
MODE2
H
L
H
L
LCD drive
output pins
300-out
263-out
256-out
Non-output pins
⎯
G133 to G169 (V
EE
level )
G129 to G172 (V
EE
level )
⎯
XDON
I
Display-ON input pin
When XDON = low, the V
GG
voltage is output all output pins irrespective of the shift data and the
content of input data. After, the contents of the shift registers becomes unfixed the data.
XON operates asynchronously with CPV. This pin is pulled-up to the V
DD
.
Since all LCD drive outputs output (G1 to G300) the V
GG
level, much current may generate them
momentarily.
When 263 / 256-pin mode, unapplied LCD panel drive pins fixed V
EE
.
The voltage applied to this pin must be a DC-level voltage that is either high (V
DD
) or low (V
SS
).
LCD panel drive pins
These pins output the shift register data or the voltage of V
GG
or V
EE
depending on the control
signals
OE
and XDON.
Power supply for LCD drive
Power supply for LCD drive
Power supply for the internal logic
The (V
DD
) is the MODE1, MODE2 and U/D pin for connection.
Power supply for the internal logic
The (V
SS
) is the MODE1, MODE2 and U/D pin for connection.
G1 to G300
V
GG
V
EE
V
DD
V
SS
O
⎯
⎯
⎯
⎯
5
2006-09-20
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