8714008DKILF datasheet, PDF - EEWORLD Datasheet

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8714008DKILF: DescriptionClock Generators & Support Products Femtoclock; Categorylogic logic; File Size445KB，34 Pages; ManufacturerIDT (Integrated Device Technology); Environmental Compliance

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8714008DKILF Overview

Clock Generators & Support Products Femtoclock

8714008DKILF Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	IDT (Integrated Device Technology)
Parts packaging code	VFQFPN
package instruction	VFQFN-56
Contacts	56
Manufacturer packaging code	NLG56P3
Reach Compliance Code	compliant
ECCN code	EAR99
series	8714008
Input adjustment	DIFFERENTIAL
JESD-30 code	S-XQCC-N56
JESD-609 code	e3
length	8 mm
Logic integrated circuit type	PLL BASED CLOCK DRIVER
Humidity sensitivity level	3
Number of functions	1
Number of inverted outputs
Number of terminals	56
Actual output times	8
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Output characteristics	OPEN-EMITTER
Package body material	UNSPECIFIED
encapsulated code	HVQCCN
Encapsulate equivalent code	LCC56,.31SQ,20
Package shape	SQUARE
Package form	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn)
Terminal form	NO LEAD
Terminal pitch	0.5 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	8 mm
minfmax	165 MHz
Base Number Matches	1

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FemtoClock

Zero Delay Buffer/ Clock

Generator for PCI Express™ and Ethernet

General Description

The ICS8714008I is Zero-Delay Buffer/Frequency Multiplier with

eight differential HCSL output pairs, and uses external feedback

(differential feedback input and output pairs) for “zero delay” clock

regeneration. In PCI Express and Ethernet applications, 100MHz

and 125MHz are the most commonly used reference clock

frequencies and each of the eight output pairs can be independently

set for either 100MHz or 125MHz. With an output frequency range of

98MHz to 165MHz, the device is also suitable for use in a variety of

other applications such as Fibre Channel (106.25MHz) and XAUI

(156.25MHz). The M-LVDS Input/Output pair is useful in backplane

applications when the reference clock can either be local (on the

same board as the ICS8714008I) or remote via a backplane

connector. In output mode, an input from a local reference clock

applied to the CLK, nCLK input pins is translated to M-LVDS and

driven out to the MLVDS, nMLVDS pins. In input mode, the internal

M-LVDS driver is placed in High-impedance state using the

OE_MLVDS pin and MLVDS, nMLVDS pin then becomes an input

(e.g. from a backplane).

The ICS8714008I uses very low phase noise FemtoClock

technology, thus making it ideal for such applications as PCI Express

Generation 1, 2 and 3 as well as for Gigabit Ethernet, Fibre Channel,

and 10 Gigabit Ethernet. It is packaged in a 56-VFQFN package

(8mm x 8mm).

ICS8714008I

DATASHEET

Features

•

Eight 0.7V differential HCSL output pairs, individually selectable

for 100MHz or 125MHz for PCIe and Ethernet applications

One differential clock input pair CLK, nCLK can accept the

following differential input levels: LVPECL, LVDS, M-LVDS,

LVHSTL, HCSL

One M-LVDS I/O pair (MLVDS, nMLVDS)

Output frequency range: 98MHz - 165MHz

Input frequency range: 19.6MHz - 165MHz

VCO range: 490MHz - 660MHz

PCI Express (2.5 Gb/s), Gen 2 (5 Gb/s), and Gen 3 (8 Gb/s)

jitter compliant

External feedback for “zero delay” clock regeneration

RMS phase jitter @ 125MHz (1.875MHz – 20MHz):

0.59ps (typical)

Full 3.3V supply mode

-40°C to 85°C ambient operating temperature

Lead-free (RoHs 6) packaging

Pin Assignment

PDIV0

nCLK

CLK

DDA

QDIV4

QDIV5

QDIV6

QDIV7

nQ0

PDIV1

nQ1

56 55 54 53 52 51 50 49 48 47 46 45 44 43

OE_MLVDS

MLVDS

nMLVDS

GND

PLL_SEL

FBO_DIV

OE0

OE1

OE2

GND

FBI_DIV0

17 18

nFBIN

FBIN

nQ2

nQ3

nQ4

nQ5

FBOUT

nFBOUT

IREF

QDIV0

QDIV1

24 25

nQ7

27 28

nQ6

ICS8714008I

56-Lead VFQFN

8mm x 8mm x 0.925mm package body

4.5mm x 5.2mm ePad size

K Package

Top View

ICS8714008DKI REVISION A NOVEMBER 25, 2013

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