Data Sheet
FEATURES
Fast throughput rate: 1 MSPS
Specified for V
DD
of 2.35 V to 5.25 V
Low power
3.6 mW at 1 MSPS with 3 V supplies
12.5 mW at 1 MSPS with 5 V supplies
Wide input bandwidth
71 dB SNR at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
High speed serial interface
SPI/QSPI™/MICROWIRE/DSP compatible
Standby mode: 1 µA maximum
6-lead SC70 package
8-lead MSOP
Qualified for automotive applications
2.35 V to 5.25 V, 1 MSPS,
12-/10-/8-Bit ADCs in 6-Lead SC70
AD7476A/AD7477A/AD7478A
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
IN
T/H
12-/10-/8-BIT
SUCCESSIVE-
APPROXIMATION
ADC
SCLK
CONTROL
LOGIC
SDATA
CS
02930-001
AD7476A/AD7477A/AD7478A
GND
Figure 1.
APPLICATIONS
Battery-powered systems
Personal digital assistants
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
High speed modems
Optical sensors
GENERAL DESCRIPTION
The
AD7476A/AD7477A/AD7478A
are 12-bit, 10-bit, and 8-bit
high speed, low power, successive-approximation analog-to-
digital converters (ADCs), respectively. The parts operate from
a single 2.35 V to 5.25 V power supply and feature throughput
rates up to 1 MSPS. The parts contain a low noise, wide
bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 13 MHz. The conversion process and
data acquisition are controlled using CS and the serial clock,
allowing the devices to interface with microprocessors or DSPs.
The input signal is sampled on the falling edge of CS, and the
conversion is also initiated at this point. There are no pipeline
delays associated with the parts. The
AD7476A/AD7477A/
AD7478A
use advanced design techniques to achieve low power
dissipation at high throughput rates. The reference for the part
is taken internally from V
DD
to allow the widest dynamic input
range to the ADC. Thus, the analog input range for the part is
0 V to V
DD
. The conversion rate is determined by the SCLK.
Rev. G
Document Feedback
PRODUCT HIGHLIGHTS
1.
2.
3.
First 12-/10-/8-bit ADCs in a SC70 package.
High throughput with low power consumption.
Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. This allows the average power consumption
to be reduced when a power-down mode is used while not
converting. The parts also feature a power-down mode to
maximize power efficiency at lower throughput rates.
Current consumption is 1 µA maximum and 50 nA
typically when in power-down mode.
Reference derived from the power supply.
No pipeline delay. The parts feature a standard successive
approximation ADC with accurate control of the sampling
instant via a CS input and once-off conversion control.
4.
5.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2002–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD7476A/AD7477A/AD7478A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7476A Specifications .............................................................. 3
AD7477A Specifications .............................................................. 5
AD7478A Specifications .............................................................. 6
Timing Specifications .................................................................. 8
Absolute Maximum Ratings.......................................................... 10
ESD Caution ................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
Circuit Information .................................................................... 15
The Converter Operation .......................................................... 15
ADC Transfer Function ............................................................. 15
Data Sheet
Typical Connection Diagram ....................................................... 16
Analog Input ............................................................................... 16
Digital Inputs .............................................................................. 17
Modes of Operation ....................................................................... 18
Normal Mode.............................................................................. 18
Power-Down Mode .................................................................... 18
Power-Up Time .......................................................................... 18
Power vs. Throughput Rate ........................................................... 20
Serial Interface ................................................................................ 21
AD7478A in a 12 SCLK Cycle Serial Interface....................... 22
Microprocessor Interfacing ........................................................... 23
AD7476A/AD7477A/AD7478A to ADSP-2181 Interface .... 23
AD7476A/AD7477A/AD7478A to DSP563xx Interface ...... 24
Application Hints ........................................................................... 25
Grounding and Layout .............................................................. 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
Automotive Products ................................................................. 27
REVISION HISTORY
1/16—Rev. F to Rev. G
Changes to Table 5 .......................................................................... 10
Changed AD7476A/AD7477A/AD7478A to ADSP-218x
Interface Section to AD7476A/AD7477A/AD7478A to
ADSP-2181 Section ........................................................................ 23
Deleted AD7476A/AD7477A/AD7478A to TMS320C541
Interface Section and Figure 28; Renumbered Sequentially ..... 23
Deleted Evaluating the AD7476A/AD7477A Performance
Section .............................................................................................. 25
Changes to Ordering Guide .......................................................... 26
1/11—Rev. E to Rev. F
Changes to Features Section ............................................................1
Changes to Ordering Guide .......................................................... 26
Added Automotive Products Section .......................................... 27
2/09—Rev. D to Rev. E
Changes to Features ..........................................................................1
Changes to Ordering Guide .......................................................... 26
4/06—Rev. C to Rev. D
Updated Format .................................................................. Universal
Changes to Ordering Guide .......................................................... 26
Rev. G | Page 2 of 28
Data Sheet
SPECIFICATIONS
AD7476A
SPECIFICATIONS
AD7476A/AD7477A/AD7478A
V
DD
= 2.35 V to 5.25 V, f
SCLK
= 20 MHz, f
SAMPLE
= 1 MSPS, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 1.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise-and-Distortion (SINAD)
3
A Grade
2
70
69
71.5
69
68
71
70
70
69
–80
–82
–84
–84
10
30
13.5
2
12
±0.75
Differential Nonlinearity
±0.75
Offset Error
Gain Error
3, 5
B Grade
2
70
69
71.5
69
68
71
70
70
69
–80
–82
–84
–84
10
30
13.5
2
12
±1.5
–0.9/+1.5
±1.5
±0.2
±1.5
±0.5
±2
0 to V
DD
±0.5
20
2.4
1.8
0.8
0.4
±0.5
±10
5
Y Grade
2
70
69
71.5
69
68
71
70
70
69
–80
–82
–84
–84
10
30
13.5
2
12
±1.5
–0.9/+1.5
±1.5
±0.2
±1.5
±0.5
±2
0 to V
DD
±0.5
20
2.4
1.8
0.8
0.4
±0.5
±10
5
Unit
dB min
dB min
dB typ
dB min
dB min
dB min
dB min
dB min
dB min
dB typ
dB typ
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
V
μA max
pF typ
V min
V min
V max
V max
μA max
nA typ
pF max
Signal-to-Noise Ratio (SNR)
3
Test Conditions/Comments
f
IN
= 100 kHz sine wave
V
DD
= 2.35 V to 3.6 V, T
A
= 25°C
V
DD
= 2.4 V to 3.6 V
V
DD
= 2.35 V to 3.6 V
V
DD
= 4.75 V to 5.25 V, T
A
= 25°C
V
DD
= 4.75 V to 5.25 V
V
DD
= 2.35 V to 3.6 V, T
A
= 25°C
V
DD
= 2.4 V to 3.6 V
V
DD
= 4.75 V to 5.25 V, T
A
= 25°C
V
DD
= 4.75 V to 5.25 V
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise (SFDR)
3
Intermodulation Distortion (IMD)
3
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
3
fa = 100.73 kHz, fb = 90.72 kHz
fa = 100.73 kHz, fb = 90.72 kHz
At 3 dB
At 0.1 dB
B and Y grades
4
Guaranteed no missed codes to 12 bits
±1.5
3, 5
±1.5
Total Unadjusted Error (TUE)
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
, CS Pin
Input Capacitance, C
IN 6
3, 5
0 to V
DD
±0.5
20
2.4
1.8
0.8
0.4
±0.5
±10
5
Track-and-hold in track; 6 pF typ when in hold
V
DD
= 2.35 V
V
DD
= 5 V
V
DD
= 3 V
Typically 10 nA, V
IN
= 0 V or V
DD
Rev. G | Page 3 of 28
AD7476A/AD7477A/AD7478A
Parameter
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
6
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
3
Throughput Rate
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Static)
Normal Mode (Operational)
Full Power-Down Mode (Static)
Full Power-Down Mode (Dynamic)
Power Dissipation
7
Normal Mode (Operational)
Full Power-Down Mode
1
2
Data Sheet
B Grade
2
Y Grade
2
Unit
V min
V max
μA max
pF max
Test Conditions/Comments
I
SOURCE
= 200 μA; V
DD
= 2.35 V to 5.25 V
I
SINK
= 200 μA
A Grade
2
V
DD
– 0.2
V
DD
– 0.2
V
DD
– 0.2
0.4
0.4
0.4
±1
±1
±1
5
5
5
Straight (Natural) Binary
800
250
1
2.35/5.25
2.5
1.2
3.5
1.7
1
0.6
0.3
17.5
5.1
5
3
800
250
1
2.35/5.25
2.5
1.2
3.5
1.7
1
0.6
0.3
17.5
5.1
5
3
800
250
1
2.35/5.25
2.5
1.2
3.5
1.7
1
0.6
0.3
17.5
5.1
5
3
ns max
ns max
MSPS max
V min/max
mA typ
mA typ
mA max
mA max
μA max
mA typ
mA typ
mW max
mW max
μW max
μW max
16 SCLK cycles
See Serial Interface section
Digital I/Ps = 0 V or V
DD
V
DD
= 4.75 V to 5.25 V, SCLK on or off
V
DD
= 2.35 V to 3.6 V, SCLK on or off
V
DD
= 4.75 V to 5.25 V, f
SAMPLE
= 1 MSPS
V
DD
= 2.35 V to 3.6 V, f
SAMPLE
= 1 MSPS
Typically 50 nA
V
DD
= 5 V, f
SAMPLE
= 100 kSPS
V
DD
= 3 V, f
SAMPLE
= 100 kSPS
V
DD
= 5 V, f
SAMPLE
= 1 MSPS
V
DD
= 3 V, f
SAMPLE
= 1 MSPS
V
DD
= 5 V
V
DD
= 3 V
Temperature ranges are as follows: A, B grades from –40°C to +85°C, Y grade from –40°C to +125°C.
Operational from V
DD
= 2.0 V, with input low voltage (V
INL
) 0.35 V maximum.
3
See the Terminology section.
4
B and Y grades, maximum specifications apply as typical figures when V
DD
= 4.75 V to 5.25 V.
5
SC70 values guaranteed by characterization.
6
Guaranteed by characterization.
7
See the Power vs. Throughput Rate section.
Rev. G | Page 4 of 28
Data Sheet
AD7477A
SPECIFICATIONS
AD7476A/AD7477A/AD7478A
V
DD
= 2.35 V to 5.25 V, f
SCLK
= 20 MHz, f
SAMPLE
= 1 MSPS, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
1
Table 2.
Parameter
DYNAMIC PERFORMANCE
Signal-to-Noise-and-Distortion (SINAD)
3
Total Harmonic Distortion (THD)
3
Peak Harmonic or Spurious Noise (SFDR)
3
Intermodulation Distortion (IMD)
3
Second-Order Terms
Third-Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
DC ACCURACY
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
3, 4
Gain Error
3, 4
Total Unadjusted Error (TUE)
3, 4
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
, SCLK Pin
Input Current, I
IN
, CS Pin
Input Capacitance, C
IN5
LOGIC OUTPUTS
Output High Voltage V
OH
Output Low Voltage, V
OL
Floating-State Leakage Current
Floating-State Output Capacitance
5
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
3
Throughput Rate
A Grade
2
61
−72
−73
−82
−82
10
30
13.5
2
10
±0.5
±0.5
±1
±1
±1.2
0 to V
DD
±0.5
20
2.4
1.8
0.8
0.4
±0.5
±10
5
Unit
dB min
dB max
dB max
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
V
µA max
pF typ
V min
V min
V max
V max
μA max
nA typ
pF max
fa = 100.73 kHz, fb = 90.7 kHz
fa = 100.73 kHz, fb = 90.7 kHz
Test Conditions/Comments
f
IN
= 100 kHz sine wave
At 3 dB
At 0.1 dB
Guaranteed no missed codes to 10 bits
Track-and-hold in track; 6 pF typ when in hold
V
DD
= 2.35 V
V
DD
= 5 V
V
DD
= 3 V
Typically 10 nA, V
IN
= 0 V or V
DD
V
DD
− 0.2
V min
0.4
V max
±1
μA max
5
pF max
Straight (Natural) Binary
700
250
1
ns max
ns max
MSPS max
I
SOURCE
= 200 μA, V
DD
= 2.35 V to 5.25 V
I
SINK
= 200 μA
14 SCLK cycles with SCLK at 20 MHz
Rev. G | Page 5 of 28
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