TB62726ANG/AFG
TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic
TB62726ANG,TB62726AFG
16-bit Constant-Current LED Driver with Operating Voltage of 3.3-V and 5-V
The TB62726A series are comprised of constant-current drivers
designed for LEDs and LED displays. The output current value
can be set using an external resistor.
As a result, all outputs will have virtually the same current
levels.
This driver incorporates 16-bit constant-current outputs, a
16-bit shift register, a 16-bit latch and a 16-bit AND-gate circuit.
These drivers have been designed using the Bi-CMOS process.
The suffix (G) appended to the part number represents a
Lead(Pb)-Free product.
TB62726ANG
TB62726AFG
Features
•
•
•
•
•
•
•
•
•
•
•
Output current capability and number of outputs:
90 mA
×
16 outputs
Constant current range: 2 to 90 mA
Application output voltage: 0.7 V (output current 2 to 80 mA)
0.4 V (output current 2 to 40 mA)
For anode-common LEDs
Input signal voltage level: 3.3-V and 5-V CMOS level (Schmitt
trigger input)
Power supply voltage range V
DD
=
3.0 to 5.5 V
Maximum output terminal voltage: 17 V
Serial and parallel data transfer rate: 20 MHz (max, cascade connection)
Operating temperature range T
opr
= −40
to 85°C
Package: Type ANG: SDIP24-P-300-1.78
Type AFG: SSOP24-P-300-1.00B
Current accuracy (All output ON)
Output Voltage
>
0.4 V
=
>
0.7 V
=
Current Accuracy
Between Bits
±4%
Between ICs
±15%
±12%
2 to 5 mA
5 to 80 mA
Output Current
Weight
SDIP24-P-300-1.78: 1.22 g (typ.)
SSOP24-P-300-1.00B: 0.32 g (typ.)
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TB62726ANG/AFG
Pin Assignment
(top view)
GND
SERIAL-IN
CLOCK
LATCH
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
V
DD
R-EXT
SERIAL-OUT
ENABLE
OUT15
OUT14
OUT13
OUT12
OUT11
OUT10
OUT9
OUT8
Warnings: Short-circuiting an output terminal to GND or to the power supply terminal may broken the device.
Please take care when wiring the output terminals, the power supply terminal and the GND terminals.
Block Diagram
OUT0
OUT1
OUT15
R-EXT
I-REG
ENABLE
Q
ST
LATCH
D
ST
Q
D
ST
Q
D
SERIAL-IN
D
CK
Q
D
CK
Q
D
CK
Q
SERIAL-OUT
CLOCK
Truth Table
CLOCK
LATCH
ENABLE
SERIAL-IN
OUT0
…
OUT7
…
OUT15
Dn
…
Dn
−
7
…
Dn
−
15
No change
Dn
+
2
…
Dn
−
5
…
Dn
−
13
Dn
+
2
…
Dn
−
5
…
Dn
−
13
OFF
SERIAL-OUT
Dn
−
15
Dn
−
14
Dn
−
13
Dn
−
13
Dn
−
13
H
L
H
X
X
L
L
L
L
H
Dn
Dn
+
1
Dn
+
2
Dn
+
3
Dn
+
3
Note 1:
OUT0 to OUT15
=
On when Dn
=
H; OUT0 to OUT15
=
Off when Dn
=
L.
In order to ensure that the level of the power supply voltage is correct, an external resistor must be connected
between R-EXT and GND.
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2006-06-14
TB62726ANG/AFG
Timing Diagram
n
=
0
CLOCK
0V
3.3 V/5 V
SERIAL-IN
0V
3.3 V/5 V
LATCH
0V
3.3 V/5 V
0V
On
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
3.3 V/5 V
ENABLE
OUT0
Off
On
OUT1
Off
On
OUT3
Off
On
OUT15
Off
3.3 V/5 V
SERIAL-OUT
0V
Warning: Latch circuit is leveled-latch circuit. Be careful because it is not triggered-latch circuit.
Note 2: The latches circuit holds data by pulling the LATCH terminal Low.
And, when LATCH terminal is a High level, latch circuit doesn’t hold data, and it passes from the input to
the output.
When ENABLE terminal is a Low level, output terminal OUT0 to OUT15 respond to the data, and on
and off does.
And, when ENABLE terminal is a High level, it offs with the output terminal regardless of the data.
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TB62726ANG/AFG
Terminal Description
Pin No.
1
2
3
4
5 to 20
Pin Name
GND
SERIAL-IN
CLOCK
LATCH
GND terminal for control logic
Input terminal for serial data for data shift register
Input terminal for clock for data shift on rising edge
Input terminal for data strobe
When the LATCH input is driven High, data is not latched. When it is pulled Low, data is
latched.
Function
OUT0 to OUT15 Constant-current output terminals
Input terminal for output enable.
21
ENABLE
All outputs ( OUT0 to OUT15 ) are turned off, when the ENABLE terminal is driven High.
And are turned on, when the terminal is driven Low.
22
23
24
SERIAL-OUT
R-EXT
V
DD
Output terminal for serial data input on SERIAL-IN terminal
Input terminal used to connect an external resistor. This regulated the output current.
3.3-V/5-V supply voltage terminal
Equivalent Circuits for Inputs and Outputs
1.
ENABLE
terminal
R (UP)
V
DD
2.
LATCH
terminal
V
DD
LATCH
ENABLE
GND
GND
R (DOWN)
3. CLOCK, SERIAL-IN terminal
V
DD
4. SERIAL-OUT terminal
V
DD
CLOCK,
SERIAL-IN
SERIAL-OUT
Internal data
GND
GND
5.
OUT0
to
OUT15
terminals
OUT0
to OUT15
Parasitic Diode
GND
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TB62726ANG/AFG
Absolute Maximum Ratings
(T
opr
=
25°C)
Characteristics
Supply voltage
Input voltage
Output current
Output voltage
ANG-type
(when not mounted)
Power dissipation ANG-type (on PCB)
(Note 3) AFG-type
(when not mounted)
AFG-type (on PCB)
ANG-type
(when not mounted)
Thermal resistance ANG-type (on PCB)
(Note 3) AFG-type
(when not mounted)
AFG-type (on PCB)
Operating temperature
Storage temperature
T
opr
T
stg
Symbol
V
DD
V
IN
I
OUT
V
OUT
P
d1
1.78
W
0.83
P
d2
1.00
104
R
th (j-a) 1
70
°C/W
140
R
th (j-a) 2
120
Rating
6
Unit
V
V
mA/ch
V
−
0.2 to V
DD
+
0.2
+
90
−
0.2 to 17
1.25
−
40 to 85
−
55 to 150
°C
°C
Note 3: ANG-Type: Powers dissipation is derated by 14.28 mW/°C if device is mounted on PCB and ambient
temperature is above 25°C.
AFG-Type: Powers dissipation is derated by 6.67 mW/°C if device is mounted on PCB and ambient
temperature is above 25°C.
With device mounted on glass-epoxy PCB of less than 40% Cu and of dimensions
50 mm
×
50 mm
×
1.6 mm.
Recommended Operating Conditions
(T
opr
=
−
40°C to 85°C unless otherwise specified)
Characteristics
Supply voltage
Output voltage
Symbol
V
DD
V
OUT
I
OUT
Output current
I
OH
I
OL
V
IH
Input voltage
V
IL
Clock frequency
LATCH pulse width
CLOCK pulse width
ENABLE pulse width
(Note 4)
Set-up time for CLOCK terminal
Hold time for CLOCK terminal
Set-up time for LATCH terminal
f
CLK
t
wLAT
t
wCLK
t
wENA
t
SETUP1
t
HOLD
t
SETUP2
Cascade connected
Each DC 1 circuit
SERIAL-OUT
SERIAL-OUT
Conditions
Min
3
Typ.
Max
5.5
4
80
Unit
V
V
mA/ch
mA
⎯
⎯
⎯
0.7
⎯
2
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0.7
×
V
DD
−
1
1
V
DD
+
0.15
0.3
×
V
DD
20
⎯
V
−
0.15
⎯
50
MHz
ns
ns
ns
ns
ns
ns
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Upper I
OUT
=
20 mA
Lower I
OUT
=
20 mA
25
2000
3000
10
⎯
10
50
Note 4: When the pulse of the Low level is inputted to the ENABLE terminal held in the High level.
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2006-06-14
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