SSTV16857 • SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset
September 2000
Revised June 2005
SSTV16857 • SSTVN16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with
184 and 232 pin PC1600, 2100, and 2700 DDR DIMM
applications. The SSTVN16857 is a 14-bit register
designed for use with 184 and 232 pin PC3200 DDR DIMM
applications. These devices have a differential input clock,
SSTL-2 compatible data inputs and a LVCMOS compatible
RESET input. These devices have been designed for com-
pliance with the JEDEC DDR module and register specifi-
cations.
The devices are fabricated on an advanced submicron
CMOS process and are designed to operate at power sup-
plies of less than 3.6V’s.
Features
s
Compliant with DDR-I registered module specifications
s
Operates at 2.5V
r
0.2V V
DD
s
SSTL-2 compatible input and output structure
s
Differential SSTL-2 compatible clock inputs
s
Low power mode when device is reset
s
Industry standard 48 pin TSSOP package
Ordering Code:
Order Number
SSTV16857MTD
SSTVN16857MTD
(Preliminary)
Package Number
MTD48
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
Q
1
-Q
14
D
1
-D
14
RESET
CK
CK
V
REF
V
DDQ
V
DD
Description
SSTL-2 Compatible Output
SSTL-2 Compatible Inputs
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
Negative Master Clock Input
Voltage Reference Pin for SSTL Level Inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
Truth Table
RESET
L
H
H
H
H
D
n
X or
Floating
L
H
X
X
CK
X or
Floating
CK
X or
Floating
Q
n
L
L
H
Q
n
Q
n
n
n
L
H
p
p
H
L
L Logic LOW
H Logic HIGH
X Don’t Care, but not floating unless noted
n
LOW-to-HIGH Clock Transition
p
HIGH-to-LOW Clock Transition
© 2005 Fairchild Semiconductor Corporation
DS500387
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SSTV16857 • SSTVN16857
Functional Description
The SSTV16857 and SSTVN16587 are 14-bit registers
with SSTL-2 compatible inputs and outputs. Input data is
captured by the register on the positive edge crossing of
the differential clock pair.
When the LV-CMOS RESET signal is asserted LOW, all
outputs and internal registers are asynchronously placed
into the LOW logic state. In addition, the clock and data dif-
ferential comparators are disabled for power savings. Out-
put glitches are prevented by disabling the internal
registers more quickly than the input comparators. When
RESET is removed, the system designer must insure the
clock and data inputs to the device are stable during the
rising transition of the RESET signal.
The SSTL-2 data inputs transition based on the value of
V
REF
. V
REF
is a stable system reference used for setting
the trip point of the input buffers of the SSTV16857/
SSTVN16857 and other SSTL-2 compatible devices.
The RESET signal is a standard CMOS compatible input
and is not referenced to the V
REF
signal.
Logic Diagram
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2
SSTV16857 • SSTVN16857
Absolute Maximum Ratings
(Note 1)
Supply Voltage (V
DDQ
)
Supply Voltage (V
DD
)
Reference Voltage (V
REF
)
Input Voltage (V
I
)
Output Voltage (V
O
)
Outputs Active (Note 2)
DC Input Diode Current (I
IK
)
V
I
0V
V
I
!
V
DD
DC Output Diode Current (I
OK
)
V
O
0V
V
O
!
V
DD
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
DD
or Ground Current
per Supply Pin (I
DD
or Ground)
Storage Temperature Range (T
stg
)
0.5V to
3.6V
0.5V to
3.6V
0.5V to
3.6V
0.5V to V
DD
0.5V
0.5V to V
DDQ
0.5V
50 mA
50 mA
50 mA
50 mA
r
50 mA
r
100 mA
65
q
C to
150
q
C
Recommended Operating
Conditions
(Note 3)
Power Supply (V
DDQ
)
SSTV16857
SSTVN16857
Power Supply (V
DD
)
Operating Range
Reference Supply (V
REF
SSTV16857
SSTVN16857
Termination Voltage (V
TT
)
Input Voltage
Output Voltage (V
O
)
Output in Active States
Output Current I
OH
/I
OL
V
DD
2.3V to 2.7V
SSTV16857
0V to V
DDQ
V
DDQ
/2)
1.15 to 1.35
1.25 to 1.35
V
REF
r
40 mV
0V to V
DD
V
DDQ
to 2.7V
2.3V to 2.7V
2.5V to 2.7V
r
20 mA
V
DD
2.5V to 2.7V
SSTVN16857
r
20 mA
0
q
C to
70
q
C
Free Air Operating Temperature (T
A
)
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the “Electrical
Characteristics” table are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
IO Absolute Maximum Rating must be observed.
Note 3:
The RESET input of the device must be held at V
DD
or GND to
ensure proper device operation. The differential inputs must not be floating,
unless RESET is asserted LOW.
DC Electrical Characteristics (SSTV16857)
(2.3V
d
V
DD
d
2.7V)
Symbol
V
IKL
V
IKH
V
IH-AC
V
IL-AC
V
IH-DC
V
IL-DC
V
IH
V
IL
V
ICR
V
I(PP)
V
OH
V
OL
I
I
I
DD
Parameter
Input LOW Clamp Voltage
Input HIGH Clamp Voltage
AC HIGH Level Input Voltage
AC LOW Level Input Voltage
DC HIGH Level Input Voltage
DC LOW Level Input Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Common Mode Input Voltage Range
Peak to Peak Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
Input Leakage Current
Static Standby
Static Operating
I
I
I
I
Conditions
V
DD
(V)
2.3
2.3
V
REF
310mV
V
REF
310mV
V
REF
150mV
V
REF
150mV
1.7
0.7
0.97
360
2.3 to 2.7
2.3
2.3 to 2.7
2.3
2.7
0
0
2.7
25
mA
V
DD
0.2
1.95
0.2
0.35
1.53
Min
Max
Units
V
V
V
V
V
V
V
V
V
mV
V
V
18 mA
18 mA
1.2
3.5
Data Inputs
Data Inputs
Data Inputs
Data Inputs
RESET
RESET
CLK, CLK
CLK, CLK
I
OH
I
OH
I
OL
I
OL
V
I
100
P
A
16 mA
100
P
A
16 mA
V
DD
or GND
GND, I
O
V
DD
, I
O
r
5.0
10
P
A
P
A
RESET
RESET
V
I
V
IH(AC)
or V
IL(AC)
3
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SSTV16857 • SSTVN16857
DC Electrical Characteristics (SSTV16857)
Symbol
I
DDD
Parameter
Dynamic Operating Current
Clock Only
RESET
V
I
Conditions
V
DD
, I
O
0
(Continued)
V
DD
(V)
Min
Max
Units
V
IH(AC)
or V
IL(AC)
90
P
A/MHz
CK, CK Duty Cycle 50%
Dynamic Operating Current
per Data Input
RESET
V
I
V
DD
, I
O
0
2.7
15
V
IH(AC)
or V
IL(AC)
CK, CK Duty Cycle 50%
Data Input
R
OH
R
OL
R
O
'
Output HIGH On Resistance
Output LOW On Resistance
| R
OH
- R
OL
|
I
OH
I
OL
I
O
½ Clock
2.3 to 2.7
2.3 to 2.7
25
q
C
2.5
7
7
Rate 50% Duty Cycle
P
A/MHz
20 mA
20 mA
20 mA, T
A
20
20
4
:
:
:
DC Electrical Characteristics (SSTVN16857)
(2.5V
d
V
DD
d
2.7V)
Symbol
V
IKL
V
IKH
V
IH-AC
V
IL-AC
V
IH-DC
V
IL-DC
V
IH
V
IL
V
ICR
V
I(PP)
V
OH
V
OL
I
I
I
DD
Parameter
Input LOW Clamp Voltage
Input HIGH Clamp Voltage
AC HIGH Level Input Voltage
AC LOW Level Input Voltage
DC HIGH Level Input Voltage
DC LOW Level Input Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
Common Mode Input Voltage Range
Peak to Peak Input Voltage
HIGH Level Output Voltage
LOW Level Output Voltage
Input Leakage Current
Static Standby
Static Operating
I
I
I
I
Conditions
V
DD
(V)
2.5
2.5
V
REF
310mV
V
REF
310mV
V
REF
150mV
V
REF
150mV
1.7
0.7
0.97
360
2.5 to 2.7
2.5
2.5 to 2.7
2.5
2.7
0
0
2.7
25
mA
V
DD
0.2
1.95
0.2
0.35
1.53
Min
Max
Units
V
V
V
V
V
V
V
V
V
mV
V
V
18 mA
18 mA
1.2
3.5
Data Inputs
Data Inputs
Data Inputs
Data Inputs
RESET
RESET
CLK, CLK
CLK, CLK
I
OH
I
OH
I
OL
I
OL
V
I
100
P
A
16 mA
100
P
A
16 mA
V
DD
or GND
GND, I
O
V
DD
, I
O
r
5.0
10
P
A
P
A
RESET
RESET
V
I
V
IH(AC)
or V
IL(AC)
V
DD
, I
O
0
I
DDD
Dynamic Operating Current
Clock Only
RESET
V
I
V
IH(AC)
or V
IL(AC)
90
P
A/MHz
CK, CK Duty Cycle 50%
Dynamic Operating Current
per Data Input
RESET
V
I
V
DD
, I
O
0
2.7
15
V
IH(AC)
or V
IL(AC)
CK, CK Duty Cycle 50%
Data Input
R
OH
R
OL
R
O
'
Output HIGH On Resistance
Output LOW On Resistance
| R
OH
- R
OL
|
I
OH
I
OL
I
O
½ Clock
2.5 to 2.7
2.5 to 2.7
25
q
C
2.5
7
7
Rate 50% Duty Cycle
P
A/MHz
20 mA
20 mA
20 mA, T
A
20
20
4
:
:
:
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4
SSTV16857 • SSTVN16857
AC Electrical Characteristics (SSTV16857)
(Note 4)
T
A
Symbol
Parameter
V
DD
0
q
C to
70
q
C, C
L
30 pF, R
L
50
:
Units
2.5V
r
0.2V; V
DDQ
Min
f
MAX
t
W
t
ACT
(Note 5)
t
INACT
(Note 5)
t
S
t
H
t
REM
t
PHL
, t
PLH
t
PHL
t
SK(Pn-Pn)
Maximum Clock Frequency
Pulse Duration, CK, CK HIGH or LOW (Figure 2)
Differential Inputs Activation Time,
data inputs must be LOW after RESET HIGH (Figure 3)
Differential Inputs De-activation Time,
data and clock inputs must be held at valid levels
(not floating) after RESET LOW
Setup Time, Fast Slew Rate (Note 6)(Note 7) (Figure 5)
Setup Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5)
Hold Time, Fast Slew Rate (Note 6)(Note 8) (Figure 5)
Hold Time, Slow Slew Rate (Note 7)(Note 8) (Figure 5)
Reset Removal Time (Figure 7)
Propagation Delay CLK, CLK to Q
n
(Figure 4)
Propagation Delay RESET to Q
n
(Figure 6)
Output to Output Skew
0.65
0.9
0.75
0.9
10
1.1
2.8
5.0
200
ns
ns
ns
ns
ns
ps
22
ns
200
2.5
22
2.5V
r
0.2V
Max
MHz
ns
ns
Note 4:
Refer to Figure 1 through Figure 7.
Note 5:
This parameter is not production tested.
Note 6:
For data signal input slew rate
t
1 V/ns.
Note 7:
For data signal input slew rate
t
0.5 V/ns and
1 V/ns.
Note 8:
For CK, CK signals input slew rates are
t
1 V/ns.
AC Electrical Characteristics (SSTVN16857)
(Note 9)
T
A
Symbol
Parameter
V
DD
0
q
C to
70
q
C, C
L
30 pF, R
L
50
:
Units
2.5V
r
0.2V; V
DDQ
Min
f
MAX
t
W
t
ACT
(Note 5)
t
INACT
(Note 5)
t
S
t
H
t
REM
t
PHL
, t
PLH
t
PSS
t
PHL
t
SK(Pn-Pn)
Maximum Clock Frequency
Pulse Duration, CK, CK HIGH or LOW (Figure 2)
Differential Inputs Activation Time,
data inputs must be LOW after RESET HIGH (Figure 3)
Differential Inputs De-activation Time,
Data and Clock Inputs must be held at valid levels
(not floating) after RESET LOW
Setup Time, Fast Slew Rate (Note 9)(Note 12) (Figure 5)
Setup Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5)
Hold Time, Fast Slew Rate (Note 11)(Note 13) (Figure 5)
Hold Time, Slow Slew Rate (Note 12)(Note 13) (Figure 5)
Reset Removal Time (Figure 7)
Propagation Delay CLK, CLK to Q
n
(Figure 4)
Propagation Delay Simultaneous Switching CLK, CLK to Q
n
(Note 14)
Propagation Delay RESET to Q
n
(Figure 6)
Output to Output Skew
0.65
0.75
0.75
0.9
10
1.1
2.4
2.7
5.0
200
ns
ns
ns
ns
ns
ns
ps
22
ns
220
2.5
22
2.5V
r
0.2V
Max
MHz
ns
ns
Note 9:
Refer to Figure 1 through Figure 7.
Note 10:
This parameter is not production tested.
Note 11:
For data signal input slew rate
t
1 V/ns.
Note 12:
For data signal input slew rate
t
0.5 V/ns and
1 V/ns.
Note 13:
For CK, CK signals input slew rates are
t
1 V/ns.
Note 14:
Simultaneous Switching is guaranteed by characterization.
5
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