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SSTVN16857MTD

Description
14-Bit Register with SSTL-2 Compatible I/O and Reset
Categorylogic    logic   
File Size84KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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SSTVN16857MTD Overview

14-Bit Register with SSTL-2 Compatible I/O and Reset

SSTVN16857MTD Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeTSSOP
package instructionTSSOP,
Contacts48
Reach Compliance Codeunknow
seriesSSTV
JESD-30 codeR-PDSO-G48
JESD-609 codee3
length12.5 mm
Logic integrated circuit typeD FLIP-FLOP
Humidity sensitivity level2
Number of digits14
Number of functions1
Number of terminals48
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)NOT SPECIFIED
propagation delay (tpd)2.4 ns
Certification statusNot Qualified
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)2.7 V
Minimum supply voltage (Vsup)2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch0.5 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width6.1 mm
minfmax220 MHz
SSTV16857 • SSTVN16857 14-Bit Register with SSTL-2 Compatible I/O and Reset
September 2000
Revised June 2005
SSTV16857 • SSTVN16857
14-Bit Register with SSTL-2 Compatible I/O and Reset
General Description
The SSTV16857 is a 14-bit register designed for use with
184 and 232 pin PC1600, 2100, and 2700 DDR DIMM
applications. The SSTVN16857 is a 14-bit register
designed for use with 184 and 232 pin PC3200 DDR DIMM
applications. These devices have a differential input clock,
SSTL-2 compatible data inputs and a LVCMOS compatible
RESET input. These devices have been designed for com-
pliance with the JEDEC DDR module and register specifi-
cations.
The devices are fabricated on an advanced submicron
CMOS process and are designed to operate at power sup-
plies of less than 3.6V’s.
Features
s
Compliant with DDR-I registered module specifications
s
Operates at 2.5V
r
0.2V V
DD
s
SSTL-2 compatible input and output structure
s
Differential SSTL-2 compatible clock inputs
s
Low power mode when device is reset
s
Industry standard 48 pin TSSOP package
Ordering Code:
Order Number
SSTV16857MTD
SSTVN16857MTD
(Preliminary)
Package Number
MTD48
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Name
Q
1
-Q
14
D
1
-D
14
RESET
CK
CK
V
REF
V
DDQ
V
DD
Description
SSTL-2 Compatible Output
SSTL-2 Compatible Inputs
Asynchronous LVCMOS Reset Input
Positive Master Clock Input
Negative Master Clock Input
Voltage Reference Pin for SSTL Level Inputs
Power Supply Voltage for Output Signals
Power Supply Voltage for Inputs
Truth Table
RESET
L
H
H
H
H
D
n
X or
Floating
L
H
X
X
CK
X or
Floating
CK
X or
Floating
Q
n
L
L
H
Q
n
Q
n
n
n
L
H
p
p
H
L
L Logic LOW
H Logic HIGH
X Don’t Care, but not floating unless noted
n
LOW-to-HIGH Clock Transition
p
HIGH-to-LOW Clock Transition
© 2005 Fairchild Semiconductor Corporation
DS500387
www.fairchildsemi.com

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