The LC709004A is a peripheral IC dedicated for expanding the capability of the microcontroller (MCU) I/O ports. It
interfaces with the microcontroller through synchronous serial communication. Communication with the extended I/O
ports is accomplished through 16-bit parallel I/O. The extended port features include the capabilities to specify the I/O
direction on a bit basis, to specify the output type (CMOS or N-channel open drain), and to specify the I/O voltage
level on a port basis according to the power level of the peripheral equipment. These features make allow the
LC709004A to be used in a wide variety of applications.
Features
•
4-/5-wire synchronous serial transmission and reception, and 16-bit parallel I/O
•
Wide operating voltage range (2.0V to 6.0V)
•
Multifunction I/O ports
- I/O direction specification: Bit units
- CMOS or Nch-OD output type specification: Bit units
- Output voltage adjustment: Port (8 bits) units
•
Output current: 12mA max. (capable of driving a green LED directly)
•
Data transmission and reception: Can control reception of input data and transmission of output data in parallel.
•
Cascaded configuration: Ports can be expanded in units of 16 bits
×
n (n is the number of LSI chips).
•
Packaging from: MFP24S (300mil): lead-free type (discontinued)
MFP24SJ (300mil): lead-free type
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.0.22
20812HKIM 20120120-S00005 No.A0165-1/13
LC709004A
Specifications
Absolute Maximum Ratings
at Ta = 25°C, VSS = 0V
Ratings
Parameter
Maximum supply voltage
Input voltage
Output voltage
Input/output voltage
Symbol
VDD max
VI
VO
VIO(1)
VIO(2)
High level output current
Peak output current
IOPH(1)
IOPH(2)
Mean output current
(Note 1)
Total output current
IOMH(1)
IOMH(2)
IOP0H
IOP1H
IOAH
Low level output current
Peak output current
IOPL(1)
IOPL(2)
Mean output current
(Note 1)
Total output current
IOML(1)
IOML(2)
IOP0L
IOP1L
IOAL
Power dissipation
Pd max (1)
Pd max (2)
Operating temperature
Storage temperature
Topr
Tstg
Ports 0 to 1
DOUT
ports 0 to 1
DOUT
Port 0
Port 1
DOUT, ports 0 to 1
MFP24S (300mil)
MFP24SJ (300mil)
-30
-55
Per 1 applicable
pin
Per 1 applicable
pin
Total of all
applicable pins
Total of all
applicable pins
Total of all
applicable pins
Ta=-30 to +70°C
16
13
7
6
32
32
77
177
mW
T.B.D
70
125
°C
mA
Ports 0 to 1
DOUT
Ports 0 to 1
DOUT
Port 0
Port 1
DOUT, ports 0 to 1
CMOS output
selected Per 1
applicable pin
CMOS output
selected Per 1
applicable pin
Total of all
applicable pins
Total of all
applicable pins
Total of all
applicable pins
-6
mA
-32
-32
-77
-13
-3
-7
Pin/Remarks
VDD, VDDP1
RES, CS, DIN,
CLK
DOUT
Port 0
Port 1
Conditions
VDD=VDDP1
VDD[V]
min
-0.3
-0.3
-0.3
-0.3
-0.3
typ
max
+7.0
VDD+0.3
VDD+0.3
VDDP1
+0.3
VDDP1
+0.3
V
Unit
Note 1: The mean output current is a mean value measured over 100ms.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A0165-2/13
LC709004A
Allowable Operating Conditions
at Ta = -30 to +70°C, VSS = 0V
Specification (Note 3)
Parameter
Operating supply voltage
Symbol
VDD(1)
VDD(2)
Pin/Remarks
VDD
VDDP1
Supply voltage must
be within VDD (1)'s
specification.
High level input voltage
VIH(1)
VIH(2)
VIH(3)
VIH(4)
Low level input voltage
VIL(1)
VIL(2)
VIL(3)
VIL(4)
DIN, ports 0 to 1
DIN, ports 0 to 1
RES, CS, CLK
RES, CS, CLK
DIN, ports 0 to 1
DIN, ports 0 to 1
RES, CS, CLK
RES, CS, CLK
4.5 to 6.0
2.0 to 6.0
4.5 to 6.0
2.0 to 6.0
4.5 to 6.0
2.0 to 6.0
4.5 to 6.0
2.0 to 6.0
0.3VDD+0.7
0.3VDD+0.7
0.4VDD+0.7
0.4VDD+0.7
VSS
VSS
VSS
VSS
VDDPx
VDDPx
VDD
VDD
0.2VDD+0.1
0.2VDD+0.1
0.1VDD+0.2
0.1VDD+0.2
V
2.0 to 6.0
VDD-3.0
VDD
Conditions
VDD[V]
min
2.0
typ
max
6.0
Unit
Note 3: VDDPx denote the power supply pin (VDDP1) for port pins.
Electrical Characteristics
at Ta = -30 to +70°C, VSS = 0V
(Note 3)
Parameter
High level input
current
Lower level input
current
High level output
voltage
VOH(1)
VOH(2)
VOH(3)
VOH(4)
VOH(5)
VOH(6)
VOH(7)
VOH(8)
VOH(9)
Lower level output
voltage
VOL(1)
VOL(2)
VOL(3)
VOL(4)
VOL(5)
VOL(6)
VOL(7)
VOL(8)
VOL(9)
Pull-up resistance
Voltage hysteresis
Consumption current
(operation stopped)
Rpu(1)
VHIS
IDDSP
CS
RES, CS, CLK
VDD=VDDP1
RES=CS=VDD
CLK=DIN=VDD or VSS
DOUT=open
P0 to P1=open or VDD
or VSS
(Note 2)
Pin capacity
CP
All pins
Other than test pin
VIN=VSS
f=1MHz
Ta=25°C
2.0 to 6.0
10
pF
2.0 to 6.0
20
μA
DOUT
Ports 1
Ports 0
DOUT
Ports 1
IIL
Symbol
IIH
Pin/Remarks
RES, CS, CLK,
Ports 0 to 1
RES, CS, CLK,
Ports 0 to 1
Ports 0
Conditions
VIN=VDD
(including output Tr.
off leakage current)
VIN=VSS
(including output Tr.
off leakage current)
IOH=-2mA
IOH=-5mA
IOH=-1mA
IOH=-2mA
IOH=-5mA
IOH=-1mA
IOH=-5mA
IOH=-10mA
IOH=-2mA
IOL=5mA
IOL=12mA
IOL=2mA
IOL=5mA
IOL=12mA
IOL=2mA
IOL=5mA
IOL=10mA
IOL=2mA
VOH=VSS
2.0 to 6.0
2.0 to 6.0
2.0 to 6.0
2.0 to 6.0
2.0 to 6.0
2.0 to 6.0
4.5 to 6.0
4.5 to 6.0
2.0 to 6.0
4.5 to 6.0
4.5 to 6.0
2.0 to 6.0
4.5 to 6.0
4.5 to 6.0
2.0 to 6.0
4.5 to 6.0
4.5 to 6.0
2.0 to 6.0
4.5 to 6.0
2.0 to 6.0
100
230
0.1VDD
2.0 to 6.0
2.0 to 6.0
2.0 to 6.0
4.5 to 6.0
4.5 to 6.0
2.0 to 6.0
4.5 to 6.0
4.5 to 6.0
2.0 to 6.0
4.5 to 6.0
4.5 to 6.0
2.0 to 6.0
VDDPx-0.5
VDDPx-1.0
VDDPx-0.5
VDDPx-0.5
VDDPx-1.0
VDDPx-0.5
VDDPx-0.5
VDDPx-1.0
VDDPx-0.5
0.4
1
0.4
0.4
1
0.4
0.4
1
0.4
650
kΩ
V
V
2.0 to 6.0
-10
VDD[V]
2.0 to 6.0
VDDPx[V]
min
Ratings
typ
max
Unit
10
μA
Note 2: The consumption current does not include the current flowing into the port's output transistor.
Note 3: VDDPx denote the power supply pin (VDDP1) for port pins.
No.A0165-3/13
LC709004A
Switching I/O Characteristics
at Ta=-30 to +70°C, VDD=VDDP1, VSS=0V
Specification (Note 3)
Parameter
Clock setup time
Symbol
TsCLK
Pin/Remarks
CS, CLK
Conditions
•Specified
with
respect to falling
edge of CS.
•See
Fig. 8.
Chip select low level setup
time
TslCS
CS, CLK
•Specified
with
respect to falling
edge of CS.
•See
Fig. 8.
Chip select low level hold
time
ThlCS
CS, CLK
•Specified
with
respect to falling
edge of CS.
•See
Fig. 8.
Clock hold time
ThCLK
CS, CLK
•Specified
with
respect to falling
edge of CS.
•See
Fig. 8.
Clock low level pulse width
TwlCLK
CLK
•See
Fig. 8.
4.5 to 6.0
2.7 to 6.0
2.0 to 6.0
Clock high level pulse
width
TwhCLK
CLK
•See
Fig. 8.
4.5 to 6.0
2.7 to 6.0
2.0 to 6.0
Chip select high level
setup time
Chip select high level hold
time
Chip select low level pulse
width
Reset low level pulse width
Data setup time
TwlRES
TsDIN
CS, RES
DIN
•See
Fig. 8.
•Specified
with
respect to falling
edge of CLK.
•See
Fig. 8.
Data hold time
ThDIN
DIN
•Specified
with
respect to falling
edge of CLK.
•See
Fig. 8.
Serial data output delay
time
(Note 4)
Port data output delay time
TdPOUT
Port 0 to 1
TdD0UT
DOUT
•Specified
with
respect to falling
edge of CLK.
•See
Fig. 8.
•Specified
with
respect to rising
edge of CS.
•See
Fig. 8.
Port data input setup time
TsPIN
Port 0 to 1
•Specified
with
respect to rising
edge of CLK.
•See
Fig. 8.
Port data input hold time
ThPIN
Port 0 to 1
•Specified
with
respect to rising
edge of CLK.
•See
Fig. 8.
TwlCS
CS, RES
•See
Fig. 8.
ThhCS
CS, RES
•See
Fig. 8.
TshCS
CS, RES
•See
Fig. 8.
2.0 to 6.0
2.0 to 6.0
2.0 to 6.0
2.0 to 6.0
4.5 to 6.0
2.0 to 6.0
4.5 to 6.0
2.7 to 6.0
2.0 to 6.0
4.5 to 6.0
2.7 to 6.0
2.0 to 6.0
4.5 to 6.0
2.7 to 6.0
2.0 to 6.0
4.5 to 6.0
2.0 to 6.0
4.5 to 6.0
2.7 to 6.0
2.0 to 6.0
30
50
50
150
300
250
500
1000
250
500
1000
200
100
ns
200
150
30
50
50
150
300
200
400
800
200
400
800
2.0 to 6.0
200
2.0 to 6.0
100
2.0 to 6.0
100
2.0 to 6.0
100
VDD[V]
min
typ
max
Unit
Note 4: The input data of P00 will be out from DOUT terminal at the first negative edge of CLK signal. Because of this,
Serial data output delay time of the first clock will be the time measured from the negative edge of the CLK or
the time at the input data (P00) is settled.
No.A0165-4/13
LC709004A
Package Dimensions
unit : mm (typ)
3112B
12.5
24
13
Package Dimensions
unit : mm (typ)
3419
13.0
24
5.4
7.6
6.0
8.0
0.63
1
1.0
(0.75)
0.35
12
0.15
1 2
(1.0)
1.0
0.4
1.9 MAX
0.15
(1.5)
1.7max
0.1
SANYO : MFP24SJ(300mil)
SANYO : MFP24S(300mil)
Pin Assignment
DOUT
DIN
CLK
CS
VDD
RES
VSS
P17
P16
P15
P14
P13
1
2
3
4
5
6
7
8
9
10
11
12
LC709004A
24
23
22
21
20
19
18
17
16
15
14
13
P00
P01
P02
P03
P04
P05
P06
P07
VDDP1
P10
P11
P12
Top view
MFP24S (300mil): lead-free type/MFP24SJ (300mil): lead-free type
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