Not recommended for new designs.
Please use SST38VF6401/6402/6403/6404.
64 Mbit (x16) Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Not Recommended for New Designs
The SST39VF6401B / SST39VF6402B devices are 4M x16, CMOS Multi-Purpose
Flash Plus (MPF+) manufactured with proprietary, high performance CMOS
SuperFlash technology. The split-gate cell design and thick-oxide tunneling injec-
tor attain better reliability and manufacturability compared with alternate
approaches. The SST39VF6401B / SST39VF6402B write (Program or Erase)
with a 2.7-3.6V power supply. These devices conform to JEDEC standard pinouts
for x16 memories and are command set compatible with other Flash devices,
enabling customers to save time and resources in implementation.
Features
• Organized as 4M x16
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Fast Read Access Time:
– 70 ns
• Latched Address and Data
• Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Superior Reliability
– Endurance: 100,000 Cycles (Typical)
– Greater than 100 years Data Retention
• Low Power Consumption (typical values at 5 MHz)
– Active Current: 9 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode: 3 µA (typical)
• Automatic Write Timing
– Internal V
PP
Generation
• Hardware Block-Protection/WP# Input Pin
– Top Block-Protection (top 32 KWord)
for SST39VF6402B
– Bottom Block-Protection (bottom 32 KWord)
for SST39VF6401B
• End-of-Write Detection
– Toggle Bits
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard
– Flash EEPROM Pin Assignments
– Software command sequence compatibility
- Address format is 11 bits, A
10
-A
0
- Block-Erase 6th Bus Write Cycle is 30H
- Sector-Erase 6th Bus Write Cycle is 50H
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Chip-Erase Capability
• Erase-Suspend/Erase-Resume Capabilities
• Hardware Reset Pin (RST#)
• Security-ID Feature
– Microchip: 128 bits; User: 128 bits
• Packages Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TFBGA (8mm x 10mm)
• All devices are RoHS compliant
©2015-2018
www.microchip.com
DS20005008C
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Not Recommended for New Designs
Product Description
The SST39VF640xB devices are 4M x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with
proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-
oxide tunneling injector attain better reliability and manufacturability compared with alternate
approaches. The SST39VF640xB write (Program or Erase) with a 2.7-3.6V power supply. These
devices conform to JEDEC standard pin assignments for x16 memories.
Featuring high performance Word-Program, the SST39VF640xB devices provide a typical Word-Pro-
gram time of 7 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of
Program operation. To protect against inadvertent write, they have on-chip hardware and Software
Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications,
these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is
rated at greater than 100 years.
The SST39VF640xB devices are suited for applications that require convenient and economical updat-
ing of program, configuration, or data memory. For all system applications, they significantly improve
performance and reliability, while lowering power consumption. They inherently use less energy during
Erase and Program than alternative flash technologies. The total energy consumed is a function of the
applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash
technology uses less current to program and has a shorter erase time, the total energy consumed
during any Erase or Program operation is less than alternative flash technologies. These devices also
improve flexibility while lowering the cost for program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and Program times, independent of the number of
Erase/Program cycles that have occurred. Therefore the system software or hardware does not have
to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Pro-
gram times increase with accumulated Erase/Program cycles.
To meet high-density, surface mount requirements, the SST39VF640xB devices are offered in 48-lead
TSOP and 48-ball TFBGA packages. See Figures 22 and 3 for pin assignments.
©2015-2018
2
DS20005008C
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Not Recommended for New Designs
Block Diagram
X-Decoder
SuperFlash
Memory
Memory Address
Address Buffer & Latches
Y-Decoder
CE#
OE#
WE#
WP#
RESET#
I/O Buffers and Data Latches
Control Logic
DQ15 - DQ0
1288 B1.0
Figure 1:
Block Diagram
©2015-2018
3
DS20005008C
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Not Recommended for New Designs
Pin Assignments
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
A21
WP#
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
Top View
Die Up
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1288 48-tsop P1.0
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
Figure 2:
Pin Assignments for 48-lead TSOP
TOP VIEW (balls facing down)
6
5
4
3
2
1
A13 A12 A14
A9
A8
A10
A15 A16 NC DQ15 VSS
A11 DQ7 DQ14 DQ13 DQ6
A19 DQ5 DQ12 VDD DQ4
A20 DQ2 DQ10 DQ11 DQ3
1288 4-tfbga B1K P2.0
WE# RST# A21
NC WP# A18
A7
A3
A17
A4
A6
A2
A5
A1
DQ0 DQ8 DQ9 DQ1
A0 CE# OE# VSS
A B C D E F G H
Figure 3:
Pin assignments for 48-ball TFBGA
©2015-2018
4
DS20005008C
64 Mbit Multi-Purpose Flash Plus
SST39VF6401B / SST39VF6402B
Not Recommended for New Designs
Table 1:
Pin Description
Symbol
A
MS1
-A
0
Pin Name
Address Inputs
Functions
To provide memory addresses.
During Sector-Erase A
MS
-A
11
address lines will select the sector.
During Block-Erase A
MS
-A
15
address lines will select the block.
DQ
15
-DQ
0
Data Input/output To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# or CE# is high.
Write Protect
Reset
Chip Enable
Output Enable
Write Enable
Power Supply
Ground
No Connection
Unconnected pins.
T1.0 25008
WP#
RST#
CE#
OE#
WE#
V
DD
V
SS
NC
To protect the top/bottom boot block from Erase/Program operation when
grounded.
To reset and return the device to Read mode.
To activate the device when CE# is low.
To gate the data output buffers.
To control the Write operations.
To provide power supply voltage: 2.7-3.6V
1. A
MS
= Most significant address
A
MS
= A
21
for SST39VF640xB
©2015-2018
5
DS20005008C
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