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70V3589S133BC

Description
SRAM 64K X 36 3.3V SYNC DP RAM
Categorystorage    storage   
File Size248KB,23 Pages
ManufacturerIDT (Integrated Device Technology)
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70V3589S133BC Overview

SRAM 64K X 36 3.3V SYNC DP RAM

70V3589S133BC Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeCABGA
package instructionBGA, BGA256,16X16,40
Contacts256
Manufacturer packaging codeBC256
Reach Compliance Codenot_compliant
ECCN code3A991.B.2.A
Samacsys DescriptionCHIP ARRAY BGA 17.0 X 1.7.0 MM X 1.0 MM
Maximum access time4.2 ns
Maximum clock frequency (fCLK)133 MHz
I/O typeCOMMON
JESD-30 codeS-PBGA-B256
JESD-609 codee0
memory density2359296 bit
Memory IC TypeMULTI-PORT SRAM
memory width36
Humidity sensitivity level3
Number of functions1
Number of ports2
Number of terminals256
word count65536 words
character code64000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX36
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA256,16X16,40
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply2.5/3.3,3.3 V
Certification statusNot Qualified
Maximum standby current0.03 A
Minimum standby current3.15 V
Maximum slew rate0.4 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn63Pb37)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
HIGH-SPEED 3.3V
128/64K x 36
SYNCHRONOUS
IDT70V3599/89S
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (12Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
BE
3L
BE
2L
BE
1L
BE
0L
BE
3R
BE
2R
BE
1R
BE
0R
FT/PIPE
L
1/0
0a 1a
a
0b 1b
b
0c 1c
c
0d 1d
d
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
a
1/0
FT/PIPE
R
R/W
L
R/W
R
CE
0L
CE
1L
1
0
1/0
B
W
0
L
B
W
1
L
B B B
WWW
2 3 3
L L R
B
W
2
R
B B
WW
1 0
R R
1
0
1 /0
CE
0R
CE
1R
OE
L
OE
R
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
1d 0d
1c 0c 1b 0b 1a 0a
a b cd
0a 1a 0b 1b
0c 1c 0d 1d
0/1
FT/PIPE
L
0/1
FT/PIPE
R
d cba
128K x 36
MEMORY
ARRAY
I/O
0L
- I/O
35 L
Din_L
Din_R
I/O
0R
- I/O
35R
CLK
L
A
16L (1)
A
0L
REPEAT
L
ADS
L
CNTEN
L
CLK
R
,
A
16R
(1)
Counter/
Address
Reg.
ADDR_L
ADDR_R
Counter/
Address
Reg.
A
0R
REPEAT
R
ADS
R
CNTEN
R
5617 tbl 01
TDI
NOTE:
1. A
16
is a NC for IDT70V3589.
JTAG
TDO
TCK
TMS
TRST
OCTOBER 2014
1
DSC 5617/10
©20104 Integrated Device Technology, Inc.
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