liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
7/30/2014
1
IS42S16400J
IS45S16400J
GENERAL DESCRIPTION
The 64Mb SDRAM is a high speed CMOS, dynamic
random-access memory designed to operate in 3.3V
memory systems containing 67,108,864 bits. Internally
configured as a quad-bank DRAM with a synchronous
interface. Each 16,777,216-bit bank is organized as 4,096
rows by 256 columns by 16 bits.
The 64Mb SDRAM includes an AUTO REFRESH MODE,
and a power-saving, power-down mode. All signals are
registered on the positive edge of the clock signal, CLK.
All inputs and outputs are LVTTL compatible.
The 64Mb SDRAM has the ability to synchronously burst
data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during
burst access.
A self-timed row precharge initiated at the end of the burst
sequence is available with the AUTO PRECHARGE function
enabled. Precharge one bank while accessing one of the
other three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
SDRAM
read and write accesses are burst oriented starting
at a selected location and continuing for a programmed
number of locations in a programmed sequence. The
registration of an ACTIVE command begins accesses,
followed by a READ or WRITE command. The ACTIVE
command in conjunction with address bits registered are
used to select the bank and row to be accessed (BA0,
BA1 select the bank; A0-A11 select the row). The READ
or WRITE commands in conjunction with address bits
registered are used to select the starting column location
for the burst access.
Programmable READ or WRITE burst lengths consist of
1, 2, 4 and 8 locations, or full page, with a burst terminate
option.
FUNCTIONAL BLOCK DIAGRAM
CLK
CKE
CS
RAS
CAS
WE
A10
DQM
COMMAND
DECODER
&
CLOCK
GENERATOR
DATA IN
BUFFER
16
16
MODE
REGISTER
12
REFRESH
CONTROLLER
DQ 0-15
SELF
REFRESH
CONTROLLER
A11
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
BA0
BA1
12
16
DATA OUT
BUFFER
V
DD
/V
DDQ
GND/GNDQ
16
REFRESH
COUNTER
4096
4096
4096
4096
ROW DECODER
MULTIPLEXER
12
MEMORY CELL
ARRAY
ROW
ADDRESS
LATCH
12
ROW
ADDRESS
BUFFER
BANK 0
SENSE AMP I/O GATE
COLUMN
ADDRESS LATCH
8
256K
(x 16)
BANK CONTROL LOGIC
BURST COUNTER
COLUMN
ADDRESS BUFFER
COLUMN DECODER
8
2
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
7/30/2014
IS42S16400J
IS45S16400J
PIN CONFIGURATION
PACKAge Code: B 54 BALL Tf-BgA (Top View) (8 mm x 8 mm Body, 0.8 mm Ball Pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
GND DQ15 GNDQ
DQ14 DQ13 VDDQ
DQ12 DQ11 GNDQ
DQ10 DQ9 VDDQ
DQ8
NC
GND
CKE
A9
A6
A4
VDDQ DQ0
GNDQ DQ2
VDDQ DQ4
GNDQ DQ6
VDD
DQ1
DQ3
DQ5
VDD DQML DQ7
CAS
BA0
A0
A3
RAS
BA1
A1
A2
WE
CS
A10
VDD
DQMH CLK
NC
A8
GND
A11
A7
A5
PIN DESCRIPTIONS
A0-A11
A0-A7
BA0, BA1
dQ0 to dQ15
CLK
CKe
CS
RAS
CAS
Row Address Input
Column Address Input
Bank Select Addresses
data I/o
System Clock Input
Clock enable
Chip Select
Row Address Strobe Command
Column Address Strobe Command
WE
LdQM, UdQM
V
dd
gNd
V
ddq
gNdQ
NC
Write enable
x16 Input/output Mask
Power
ground
Power Supply for I/o Pin
ground for I/o Pin
No Connection
Integrated Silicon Solution, Inc. — www.issi.com
Rev. G
7/30/2014
3
IS42S16400J
IS45S16400J
PIN CONFIGURATION
PACKAGE CODE: B2 60 BALL TF-BGA (Top View) (10.1 mm x 6.4 mm Body, 0.65 mm Ball Pitch)
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Embedded System
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