CY29947
2.5 V or 3.3 V, 200 MHz,
1:9 Clock Distribution Buffer
2.5 V or 3.3 V, 200 MHz, 1:9 Clock Distribution Buffer
Features
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Functional Description
The CY29947 is a low-voltage 200 MHz clock distribution buffer
with the capability to select one of two LVCMOS/LVTTL
compatible clock inputs. The two clock sources can be used to
provide for a test clock as well as the primary system clock. All
other control inputs are LVCMOS/LVTTL compatible. The 9
outputs are LVCMOS or LVTTL compatible and can drive 50
series or parallel terminated transmission lines.For series
terminated transmission lines, each output can drive one or two
traces giving the device an effective fanout of 1:18. The outputs
can also be three-stated via the three-state input TS#. Low
output-to-output skews make the CY29947 an ideal clock
distribution buffer for nested clock trees in the most demanding
of synchronous systems.
The CY29947 also provides a synchronous output enable input
for enabling or disabling the output clocks. Since this input is
internally synchronized to the input clock, potential output
glitching or runt pulse generation is eliminated.
For a complete list of related documentation,
click here.
2.5 V or 3.3 V operation
200 MHz clock support
LVCMOS-/LVTTL-compatible inputs
9 clock outputs: drive up to 18 clock lines
Synchronous Output Enable
Output three-state control
250 ps max. output-to-output skew
Pin compatible with MPC947, MPC9447
Available in Industrial and Commercial temp. range
32-pin TQFP package
Block Diagram
VDD
TCLK0
TCLK1
TCLK_SEL
SYNC_OE
TS#
0
1
VDDC
9
Q0-Q8
Cypress Semiconductor Corporation
Document Number: 38-07287 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised May 13, 2016
CY29947
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Output Enable/Disable ..................................................... 4
Maximum Ratings ............................................................. 5
DC Parameters .................................................................. 5
Thermal Resistance .......................................................... 5
AC Parameters .................................................................. 6
Ordering Information ........................................................ 8
Ordering Code Definitions ........................................... 8
Package Drawing and Dimension ................................... 9
Acronyms ........................................................................ 10
Document Conventions ................................................. 10
Units of Measure ....................................................... 10
Revision History ............................................................. 11
Sales, Solutions, and Legal Information ...................... 12
Worldwide Sales and Design Support ....................... 12
Products .................................................................... 12
PSoC®Solutions ....................................................... 12
Cypress Developer Community ................................. 12
Technical Support ..................................................... 12
Document Number: 38-07287 Rev. *H
Page 2 of 12
CY29947
Pinouts
Figure 1. 32-pin TQFP pinout
VDDC
VDDC
27
VSS
VSS
32
31
30
29
28
26
25
VSS
Q0
Q1
Q2
VSS
TCLK_SEL
TCLK0
TCLK1
SYNC_OE
TS#
VDD
VSS
1
2
3
4
5
6
7
8
CY29947
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
VSS
Q3
VDDC
Q4
VSS
Q5
VDDC
VSS
VSS
VSS
VDDC
VDDC
Pin Definitions
Pin
3
4
2
11, 13, 15, 19,
21, 23, 26, 28,
30
5
6
10, 14, 18, 22,
27, 31
7
1, 8, 9, 12, 16,
17, 20, 24, 25,
29, 32
Name
TCLK0
TCLK1
TCLK_SEL
Q(8:0)
VDDC
PWR
I/O
[1]
I, PU
I, PU
I, PU
O
Test Clock Input
Test Clock Input
Test Clock Select Input.
When LOW, TCLK0 is selected. When
asserted HIGH, TCLK1 is selected.
Clock Outputs
Description
SYNC_OE
TS#
VDDC
VDD
VSS
I, PU
I, PU
Output Enable Input.
When asserted HIGH, the outputs are enabled
and when set LOW the outputs are disabled in a LOW state.
Three-state Control Input.
When asserted LOW, the output buffers
are three-stated. When set HIGH, the output buffers are enabled.
3.3 V or 2.5 V Power Supply for Output Clock Buffers
3.3 V or 2.5 V Power Supply
Common Ground
Note
1. PD = internal pull-down, PU = internal pull-up.
Document Number: 38-07287 Rev. *H
VSS
Q8
Q7
Q6
Page 3 of 12
CY29947
Output Enable/Disable
The CY29947 features a control input to enable or disable the
outputs. This data is latched on the falling edge of the input clock.
When SYNC_OE is asserted LOW, the outputs are disabled in a
LOW state. When SYNC_OE is set HIGH, the outputs are
enabled as shown in
Figure 2.
Figure 2. SYNC_OE Timing Diagram
TCLK
SYNC_OE
Q
Document Number: 38-07287 Rev. *H
Page 4 of 12
CY29947
Maximum Ratings
Exceeding maximum ratings
[2]
may shorten the useful life of the
device. User guidelines are not tested.
Maximum Input Voltage Relative to V
SS
: ........... V
SS
– 0.3 V
Maximum Input Voltage Relative to V
DD
: ........... V
DD
+ 0.3 V
Storage Temperature: ............................. –65 °C to + 150 °C
Operating Temperature: ............................. –40 °C to +85 °C
Maximum ESD protection .............................................. 2 kV
Maximum Power Supply: .............................................. 5.5 V
Maximum Input Current: ........................................... ±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any voltage
higher than the maximum rated voltages to this circuit. For proper
operation, V
in
and V
out
should be constrained to the range:
V
SS
< (V
in
or V
out
) < V
DD
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
V
DD
= V
DDC
= 3.3 V ± 10% or 2.5 V ± 5%, Over the specified temperature range
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DDQ
I
DD
Description
Input Low Voltage
Input High Voltage
Input Low Current
[3]
Input High Current
[3]
Output Low Voltage
[4]
Output High Voltage
[4]
Quiescent Supply Current
Dynamic Supply Current
V
DD
= 3.3 V, Outputs @ 100 MHz,
CL = 30 pF
V
DD
= 3.3 V, Outputs @ 160 MHz,
CL = 30 pF
V
DD
= 2.5 V, Outputs @ 100 MHz,
CL = 30 pF
V
DD
= 2.5 V, Outputs @ 160 MHz,
CL = 30 pF
Zout
C
in
Output Impedance
Input Capacitance
V
DD
= 3.3 V
V
DD
= 2.5 V
I
OL
= 20 mA
I
OH
= –20 mA, V
DD
= 3.3 V
I
OH
= –20 mA, V
DD
= 2.5 V
Conditions
Min
V
SS
2.0
–
–
–
2.5
1.8
–
–
–
–
–
12
14
–
Typ
–
–
–
–
–
–
–
5
120
200
85
140
15
18
4
Max
0.8
V
DD
–100
10
0.4
–
–
7
–
–
–
–
18
22
–
pF
mA
mA
Unit
V
V
µA
µA
V
V
Thermal Resistance
Parameter
[5]
θ
JA
θ
JC
Description
Thermal resistance
(junction to ambient)
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
32-pin TQFP
65
12
Unit
°C/W
°C/W
Notes
2.
Multiple Supplies:
The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Inputs have pull-up/pull-down resistors that effect input current.
4. Driving series or parallel terminated 50 (or 50
to V
DD
/2) transmission lines.
5. These parameters are guaranteed by design and are not tested.
Document Number: 38-07287 Rev. *H
Page 5 of 12
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