MPC8567VTAUJJ datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> MPC8567VTAUJJ

MPC8567VTAUJJ: DescriptionMicroprocessors - MPU Non-Encrypt No PB 1.3GHz; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，139 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

Download Datasheet Parametric Compare View All

MPC8567VTAUJJ Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	MPC8567VTAUJJ	-	-	View	Buy Now

MPC8567VTAUJJ Overview

Microprocessors - MPU Non-Encrypt No PB 1.3GHz

MPC8567VTAUJJ Parametric

Parameter Name	Attribute value
Brand Name	Freescale
Is it lead-free?	Contains lead
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	BGA
package instruction	33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCPBGA-1023
Contacts	1023
Reach Compliance Code	not_compliant
ECCN code	5A992
Address bus width
bit size	32
boundary scan	YES
maximum clock frequency	166 MHz
External data bus width
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B1023
JESD-609 code	e2
length	33 mm
low power mode	YES
Humidity sensitivity level	3
Number of terminals	1023
Maximum operating temperature	105 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Encapsulate equivalent code	BGA1023,32X32,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
power supply	1.1,1.8/2.5,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	2.75 mm
speed	1333 MHz
Maximum supply voltage	1.155 V
Minimum supply voltage	1.045 V
Nominal supply voltage	1.1 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal surface	TIN COPPER/TIN SILVER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	33 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC

Preview

Download Datasheet

View All

Freescale Semiconductor

Technical Data

Document Number: MPC8568EEC

Rev. 1, 10/2010

MPC8568E/MPC8567E

PowerQUICC III

Integrated Processor

Hardware Specifications

Due to feature similarities, this document covers both the

MPC8568E and MPC8567E features. For simplicity,

MPC8568 may only be mentioned throughout the document.

The MPC8567E feature differences are as follows:

• The MPC8567E PCI-Express supports x1/x2/x4, but

does not have x8 support.

• Does not have eTSEC1, eTSEC2, or TLU

Note that both the MPC8568E and MPC8567E have their

own pin assignment tables.

10.

11.

12.

13.

14.

15.

16.

17.

18.

19.

20.

21.

22.

23.

24.

25.

26.

27.

Contents

MPC8568E Overview . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 10

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14

Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18

DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 18

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Ethernet Interface and MII Management . . . . . . . . . . 26

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . . 61

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

PIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

TDM/SI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

UTOPIA/POS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

HDLC, BISYNC, Transparent and

Synchronous UART . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Package and Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

System Design Information . . . . . . . . . . . . . . . . . . . 130

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 136

Document Revision History . . . . . . . . . . . . . . . . . . 138

MPC8568E Overview

— Byte-accessible ECC uses read-modify-write transaction accesses for smaller-than-cache-line

accesses.

1.2.2

e500 Coherency Module (ECM) and Address Map

The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus

between the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable

memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be

routed or dispatched to target modules on the device.

The MPC8568E supports a flexible 36-bit physical address map. Conceptually, the address map consists of

local space and external address space. The local address map is supported by eight local access windows

that define mapping within the local 36-bit (64-Gbyte) address space.

The MPC8568E can be made part of a larger system address space through the mapping of translation

windows. This functionality is included in the address translation and mapping units (ATMUs). Both

inbound and outbound translation windows are provided. The ATMUs allows the MPC8568E to be part of

larger address maps such as the PCI or PCI Express 64-bit address environment and the RapidIO

environment.

1.2.3

•

QUICC Engine

Integrated 8-port L2 Ethernet switch

— 8 connection ports of 10/100 Mbps MII/RMII & one CPU internal port

— Each port supports four priority levels

— Priority levels used with VLAN tags or IP TOS field to implement QoS

— QoS types of traffic, such as voice, video, and data

Includes support for the following protocols:

— ATM SAR up to 622 Mbps (OC-12) full duplex, with ATM traffic shaping (ATF TM4.1) for

up to 64K ATM connections

— ATM AAL1 structured and unstructured Circuit Emulation Service (CES 2.0)

— IMA and ATM Transmission convergence sub-layer

— ATM OAM handling features compatible with ITU-T I.610

— PPP, Multi-Link (ML-PPP), Multi-Class (MC-PPP) and PPP mux in accordance with the

following RFCs: 1661, 1662, 1990, 2686 and 3153

— IP termination support for IPv4 and IPv6 packets including TOS, TTL and header checksum

processing

— ATM (AAL2/AAL5) to Ethernet (IP) interworking

— Extensive support for ATM statistics and Ethernet RMON/MIB statistics.

— 256 channels of HDLC/Transparent or 128 channels of SS#7

Includes support for the following serial interfaces:

— Two UL2/POS-PHY interfaces with 124 Multi-PHY addresses on UTOPIA interface each or

31 Multi-PHY addresses on the POS interface each.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

•

Freescale Semiconductor

MPC8568E Overview

— Three 1-Gbps Ethernet interfaces using three GMII, two RGMII/TBI/RTBI

— Up to eight 10/100-Mbps Ethernet interfaces using MII or RMII

— Up to eight T1/E1/J1/E3 or DS-3 serial interfaces

1.2.4

Integrated Security Engine (SEC)

The SEC is a modular and scalable security core optimized to process all the algorithms associated with

IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. Although it is not a protocol processor, the SEC is

designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single pass of

the data. The version of the SEC used in the MPC8568E is specifically capable of performing single-pass

security cryptographic processing for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, and 802.11i.

• Optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and

3GPP

• Compatible with code written for the Freescale MPC8541E and MPC8555E devices

• XOR engine for parity checking in RAID storage applications.

• Four crypto-channels, each supporting multi-command descriptor chains

• Cryptographic execution units:

— PKEU—public key execution unit

— DEU—Data Encryption Standard execution unit

— AESU—Advanced Encryption Standard unit

— AFEU—ARC four execution unit

— MDEU—message digest execution unit

— KEU—Kasumi execution unit

— RNG—Random number generator

1.2.5

Enhanced Three-Speed Ethernet Controllers

The MPC8568E has two on-chip enhanced three-speed Ethernet controllers (eTSECs). The eTSECs

incorporate a media access control (MAC) sublayer that supports 10- and 100-Mbps and 1-Gbps

Ethernet/802.3 networks with MII, RMII, GMII, RGMII, TBI, and RTBI physical interfaces. The eTSECs

include 2-Kbyte receive and 10-Kbyte transmit FIFOs and DMA functions.

The MPC8568E eTSECs support programmable CRC generation and checking, RMON statistics, and

jumbo frames of up to 9.6 Kbytes. Frame headers and buffer descriptors can be forced into the L2 cache

to speed classification or other frame processing. They are IEEE Std 802.3™, IEEE 802.3u, IEEE 802.3x,

IEEE 802.3z, IEEE 802.3ac, IEEE 802.3ab-compatible.

The buffer descriptors are based on the MPC8260 and MPC860T 10/100 Ethernet programming models.

Each eTSEC can emulate a PowerQUICC III TSEC, allowing existing driver software to be re-used with

minimal change.

Some of the key features of these controllers include:

• Flexible configuration for multiple PHY interface configurations.

Table 1

lists available

configurations.

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

MPC8567VTAUJJ Related Products

	MPC8567VTAUJJ	MPC8568VTAUJJ	MPC8567VTANGG	MPC8568EVTAUJJ	MPC8568ECVTAQGG	MPC8567VTAQGG
Description	Microprocessors - MPU Non-Encrypt No PB 1.3GHz	Microprocessors - MPU 8568 1.33GHz Non Encrypt	Microprocessors - MPU 800MHz Non-Encrypt	Microprocessors - MPU No PB 1.3 GHz	Microprocessors - MPU 8568 1GHz Pb Free	Microprocessors - MPU 1GHz Non-Encrypt
Brand Name	Freescale	Freescale	Freescale	-	Freescale	-
Is it lead-free?	Contains lead	Contains lead	Contains lead	-	Contains lead	Contains lead
Is it Rohs certified?	conform to	conform to	conform to	-	conform to	conform to
Maker	NXP	NXP	NXP	-	NXP	NXP
Parts packaging code	BGA	BGA	BGA	-	BGA	BGA
package instruction	33 X 33 MM, 2.75 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, FCPBGA-1023	BGA, BGA1023,32X32,40	BGA, BGA1023,32X32,40	-	BGA, BGA1023,32X32,40	BGA, BGA1023,32X32,40
Contacts	1023	1023	1023	-	1023	1023
Reach Compliance Code	not_compliant	not_compliant	not_compliant	-	not_compliant	not_compliant
ECCN code	5A992	5A992	5A992	-	5A002.A	5A992
Address bus width	-	16	16	-	16	16
bit size	32	32	32	-	32	32
boundary scan	YES	YES	YES	-	YES	YES
External data bus width	-	64	64	-	64	64
Format	FLOATING POINT	FIXED POINT	FIXED POINT	-	FIXED POINT	FIXED POINT
Integrated cache	YES	YES	YES	-	YES	YES
JESD-30 code	S-PBGA-B1023	S-PBGA-B1023	S-PBGA-B1023	-	S-PBGA-B1023	S-PBGA-B1023
JESD-609 code	e2	e2	e2	-	e2	e2
length	33 mm	33 mm	33 mm	-	33 mm	33 mm
low power mode	YES	YES	YES	-	YES	YES
Humidity sensitivity level	3	3	3	-	3	3
Number of terminals	1023	1023	1023	-	1023	1023
Maximum operating temperature	105 °C	105 °C	105 °C	-	105 °C	105 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	BGA	BGA	BGA	-	BGA	BGA
Encapsulate equivalent code	BGA1023,32X32,40	BGA1023,32X32,40	BGA1023,32X32,40	-	BGA1023,32X32,40	BGA1023,32X32,40
Package shape	SQUARE	SQUARE	SQUARE	-	SQUARE	SQUARE
Package form	GRID ARRAY	GRID ARRAY	GRID ARRAY	-	GRID ARRAY	GRID ARRAY
Peak Reflow Temperature (Celsius)	260	260	260	-	260	260
power supply	1.1,1.8/2.5,2.5/3.3 V	1.1,1.8/2.5,2.5/3.3 V	1.1,1.8/2.5,2.5/3.3 V	-	1.1,1.8/2.5,2.5/3.3 V	1.1,1.8/2.5,2.5/3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
Maximum seat height	2.75 mm	2.75 mm	2.75 mm	-	2.75 mm	2.75 mm
speed	1333 MHz	1333 MHz	800 MHz	-	1000 MHz	1000 MHz
Maximum supply voltage	1.155 V	1.155 V	1.155 V	-	1.155 V	1.155 V
Minimum supply voltage	1.045 V	1.045 V	1.045 V	-	1.045 V	1.045 V
Nominal supply voltage	1.1 V	1.1 V	1.1 V	-	1.1 V	1.1 V
surface mount	YES	YES	YES	-	YES	YES
technology	CMOS	CMOS	CMOS	-	CMOS	CMOS
Temperature level	OTHER	OTHER	OTHER	-	INDUSTRIAL	OTHER
Terminal surface	TIN COPPER/TIN SILVER	TIN COPPER/TIN SILVER	TIN COPPER/TIN SILVER	-	TIN COPPER/TIN SILVER	TIN COPPER/TIN SILVER
Terminal form	BALL	BALL	BALL	-	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	-	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	-	BOTTOM	BOTTOM
Maximum time at peak reflow temperature	40	40	40	-	40	40
width	33 mm	33 mm	33 mm	-	33 mm	33 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC	-	MICROPROCESSOR, RISC	MICROPROCESSOR, RISC

Recommended Resources

Single and Quad Channel Linear EML Driver Series, Did You Know?

Practical power limiting controller circuit

op amp encoder

photosensitive oscillator circuit

555 zero cross circuit

Computer motherboard circuit diagram 830_48

Detailed explanation of ADC12 single channel multiple conversion program: It uses LCD1602 liquid crystal display #define Num_of_Results 32 uint results[Num_of_Results]; uchar d[11]={0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f,0x00}; uchar d1[11]={0xbf,0x86,0xdb,0xcf,0...; tcvsdonnnie Microcontroller MCU

【Mobile phone wireless charging pad based on Renesas R7F0C80212--2】: Project plan: Use R7F0C80212 as the controller. After initialization, turn on AD and detect the voltage value of the transmitting coil. When the mobile phone's wireless charging board is placed on the...; 路飞d梦想 Renesas Electronics MCUs

KSZ8993M application problem, please help: In common DM642 network development, the network port is designed by combining DM642-EMAC with the PHY layer, and then the network driver is developed using TI-NDK. In my design, DM642+ KSZ8993M was s...; gmy800101 Embedded System

【Qinheng RISC-V core CH582】 5 Bluetooth routine initial evaluation and environment construction: Qinheng provides quite a lot of Bluetooth test routines. This evaluation first builds the test environmentOpen the Peripheral example under BLE, compile and download it to the development board Downlo...; kit7828 Domestic Chip Exchange

Does anyone know how to connect the pins of ml2035 to the spi bus?: rt...; laopo163 Embedded System

Looking for an idle 2440 development board to teach a beautiful girl how to learn Linux: A beautiful colleague in the company wants to learn Linux, so she asked me to help her find a 2440 development board. If any of you have one unused, please give it to me. I am kind-hearted and want to...; lelee007 Buy&Sell

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components