EEWORLDEEWORLDEEWORLD

Part Number

Search

532BA000210BGR

Description
LVDS Output Clock Oscillator, 200MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
Categoryoscillator   
File Size2MB,33 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

532BA000210BGR Overview

LVDS Output Clock Oscillator, 200MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

532BA000210BGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
Reach Compliance Codeunknown
Is SamacsysN
Other featuresIT CAN ALSO OPERATE AT 100.00 MHZ
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number532
Installation featuresSURFACE MOUNT
Nominal operating frequency200 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeLVDS
physical size177.8mm x 127.0mm x 41.91mm
longest rise time0.35 ns
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
Si532
D
U A L
F
R E Q U E N C Y
C
R Y S TA L
O
S C I L L A T O R
(XO )
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
Two selectable output frequencies
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
FS
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si532 dual frequency XO utilizes Silicon Laboratories’ advanced
DSPLL
®
circuitry to provide a low jitter clock at high frequencies. The Si532 is
available with any-rate output frequency from 10 to 945 MHz and select
frequencies to 1400 MHz. Unlike a traditional XO where a different crystal is
required for each output frequency, the Si532 uses one fixed crystal
frequency to provide a wide range of output frequencies. This IC based
approach allows the crystal resonator to provide exceptional frequency
stability and reliability. In addition, DSPLL clock synthesis provides superior
supply noise rejection, simplifying the task of generating low jitter clocks in
noisy environments typically found in communication systems. The Si532 IC
based XO is factory configurable for a wide variety of user specifications
including frequency, supply voltage, output format, and temperature stability.
Specific configurations are factory programmed at time of shipment, thereby
eliminating long lead times associated with custom oscillators.
CLK–
CLK+
(LVDS/LVPECL/CML)
FS
OE
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
(CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
FS
OE
GND
Rev. 1.0 7/06
Copyright © 2006 by Silicon Laboratories
Si532
Looking for the driver and usage of Philips PDIUSBD12
I use 51 + PDIUSBD12 to communicate with PC. The firmware program is written, but I can't find the driver for PC winxp. I want the driver of Philips PDIUSBD12 and how to use it. If anyone knows where ...
xujualiang Embedded System
How to support media player?
Wince5.0 has added all the components related to media player, format support, and basically all multimedia. After starting, I saw that the file icons of .mpg and .wmv have changed, but the icon of .a...
hyw123456 Embedded System
Problems with using 89C2051 to replace 89c51 chip
I used 89C51 to write a clock display program. The hardware circuit has 4 separate digital tubes for display. P1.1G to P1.7 are connected to the A, B, C, D, E, F, G of the digital tubes. P2.3 is conne...
WQY_7692 Embedded System
Realization of FIR digital filter using DSP
[size=5]Using DSP to implement FIR digital filter[/size] [size=5][/size]...
fish001 DSP and ARM Processors
Where is 30-layer PCB used?
From EEWORLD cooperation group: arm linux fpga embedded 0 (49900581) Group owner: wangkj...
秋水长天 PCB Design
[Experience in using MSP430 compiler] + Share my experience and skills in using MSP430 compiler!
I have just started using IAR software. Here are some pictures, hoping to give some help and inspiration to beginners. The software installation and cracking are omitted. You can download it from the ...
sdrcust Microcontroller MCU

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2143  889  2384  2814  1661  44  18  48  57  34 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号