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LTC2206UK-14

Description
1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
CategoryAnalog mixed-signal IC    converter   
File Size1MB,32 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
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LTC2206UK-14 Overview

1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48

LTC2206UK-14 Parametric

Parameter NameAttribute value
Parts packaging codeQFN
package instructionHVQCCN,
Contacts48
Reach Compliance Codeunknow
Maximum analog input voltage2.25 V
Minimum analog input voltage-2.25 V
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-PQCC-N48
length7 mm
Maximum linear error (EL)0.0092%
Number of analog input channels1
Number of digits14
Number of functions1
Number of terminals48
Maximum operating temperature70 °C
Minimum operating temperature
Output bit codeOFFSET BINARY, 2'S COMPLEMENT BINARY
Output formatPARALLEL, WORD
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Certification statusNot Qualified
Sampling rate80 MHz
Sample and hold/Track and holdSAMPLE
Maximum seat height0.8 mm
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
width7 mm
Base Number Matches1
FEATURES
LTC2207-14/LTC2206-14
14-Bit, 105Msps/80Msps
ADCs
DESCRIPTIO
The LTC
®
2207-14/LTC2206-14 are 105Msps/80Msps,
sampling 14-bit A/D converters designed for digitizing
high frequency, wide dynamic range signals up to input
frequencies of 700MHz. The input range of the ADC can
be optimized with the PGA front end.
The LTC2207-14/LTC2206-14 are perfect for demanding
communications applications, with AC performance that
includes 77.3dB SNR and 98dB spurious free dynamic
range (SFDR). Ultralow jitter of 80fs
RMS
allows under-
sampling of high input frequencies with excellent noise
performance. Maximum DC specs include ±1.5LSB INL,
±1LSB DNL (no missing codes) over temperature.
A separate output power supply allows the CMOS output
swing to range from 0.5V to 3.6V.
The ENC
+
and ENC
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed with a wide range of
clock duty cycles.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners. Patents Pending.
Sample Rate: 105Msps/80Msps
77.3dBFS Noise Floor
98dB SFDR
SFDR >82dB at 250MHz (1.5V
P-P
Input Range)
PGA Front End (2.25V
P-P
or 1.5V
P-P
Input Range)
700MHz Full Power Bandwidth S/H
Optional Internal Dither
Optional Data Output Randomizer
Single 3.3V Supply
Power Dissipation: 947mW/762mW
Optional Clock Duty Cycle Stabilizer
Out-of-Range Indicator
Pin Compatible Family
105Msps: LTC2207 (16-Bit), LTC2207-14 (14-Bit)
80Msps: LTC2206 (16-Bit), LTC2206-14 (14-Bit)
65Msps: LTC2205 (16-Bit), LTC2205-14 (14-Bit)
40Msps: LTC2204 (16-Bit)
25Msps: LTC2203 (16-Bit) Single-Ended Clock
10Msps: LTC2202 (16-Bit) Single-Ended Clock
48-Pin 7mm
×
7mm QFN Package
APPLICATIO S
Telecommunications
Receivers
Cellular Base Stations
Spectrum Analysis
Imaging Systems
ATE
TYPICAL APPLICATIO
3.3V
SENSE
V
CM
2.2µF
1.25V
COMMON MODE
BIAS VOLTAGE
INTERNAL ADC
REFERENCE
GENERATOR
OV
DD
0.5V TO 3.6V
0.1µF
OF
CLKOUT
+
CLKOUT
D13
D0
AMPLITUDE (dBFS)
3.3V
0.1µF
0.1µF
22076 TA01
AIN
+
ANALOG
INPUT
AIN
+
S/H
AMP
CLOCK/DUTY
CYCLE
CONTROL
ENC
+
ENC
14-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC AND
SHIFT REGISTER
OUTPUT
DRIVERS
OGND
V
DD
GND
PGA
SHDN
DITH
MODE
OE
RAND
0.1µF
ADC CONTROL INPUTS
U
U
U
LTC2207-14: 32K Point FFT,
f
IN
= 14.86MHz, –1dBFS,
PGA = 0, 105Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10
30
40
20
FREQUENCY (MHz)
50
22076 TA01b
220714614fa
1

LTC2206UK-14 Related Products

LTC2206UK-14 LTC2207CUK-14 LTC2206CUK-14 LTC2207-14 LTC2207IUK-14 LTC2207UK-14 LTC2206IUK-14
Description 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48 1-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC48
length 7 mm 7 mm 7 mm 7 mm 7 mm 7 mm 7 mm
Number of digits 14 14 14 14 14 14 14
Number of functions 1 1 1 1 1 1 1
Number of terminals 48 48 48 48 48 48 48
Maximum operating temperature 70 °C 70 °C 70 °C 85 Cel 85 °C 70 °C 85 °C
Output format PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD PARALLEL, WORD
surface mount YES YES YES YES YES YES YES
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL INDUSTRIAL INDUSTRIAL COMMERCIAL INDUSTRIAL
Terminal form NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD NO LEAD
Terminal location QUAD QUAD QUAD QUAD QUAD QUAD QUAD
width 7 mm 7 mm 7 mm 7 mm 7 mm 7 mm 7 mm
Parts packaging code QFN QFN QFN - QFN QFN QFN
package instruction HVQCCN, HVQCCN, LCC48,.27SQ,20 HVQCCN, LCC48,.27SQ,20 - HVQCCN, LCC48,.27SQ,20 HVQCCN, HVQCCN, LCC48,.27SQ,20
Contacts 48 48 48 - 48 48 48
Reach Compliance Code unknow _compli _compli - _compli unknow _compli
Maximum analog input voltage 2.25 V 2.25 V 2.25 V - 2.25 V 2.25 V 2.25 V
Minimum analog input voltage -2.25 V 1.5 V 1.5 V - 1.5 V -2.25 V 1.5 V
Converter type ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD - ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD
JESD-30 code S-PQCC-N48 S-PQCC-N48 S-PQCC-N48 - S-PQCC-N48 S-PQCC-N48 S-PQCC-N48
Maximum linear error (EL) 0.0092% 0.0092% 0.0092% - 0.0092% 0.0092% 0.0092%
Number of analog input channels 1 1 1 - 1 1 1
Output bit code OFFSET BINARY, 2'S COMPLEMENT BINARY OFFSET BINARY, 2'S COMPLEMENT BINARY OFFSET BINARY, 2'S COMPLEMENT BINARY - OFFSET BINARY, 2'S COMPLEMENT BINARY OFFSET BINARY, 2'S COMPLEMENT BINARY OFFSET BINARY, 2'S COMPLEMENT BINARY
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code HVQCCN HVQCCN HVQCCN - HVQCCN HVQCCN HVQCCN
Package shape SQUARE SQUARE SQUARE - SQUARE SQUARE SQUARE
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE - CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Certification status Not Qualified Not Qualified Not Qualified - Not Qualified Not Qualified Not Qualified
Sampling rate 80 MHz 105 MHz 80 MHz - 105 MHz 105 MHz 80 MHz
Sample and hold/Track and hold SAMPLE SAMPLE SAMPLE - SAMPLE SAMPLE SAMPLE
Maximum seat height 0.8 mm 0.8 mm 0.8 mm - 0.8 mm 0.8 mm 0.8 mm
Nominal supply voltage 3.3 V 3.3 V 3.3 V - 3.3 V 3.3 V 3.3 V
technology CMOS CMOS CMOS - CMOS CMOS CMOS
Terminal pitch 0.5 mm 0.5 mm 0.5 mm - 0.5 mm 0.5 mm 0.5 mm
Base Number Matches 1 1 1 - 1 1 1
Brand Name - Linear Technology Linear Technology - Linear Technology - Linear Technology
Is it Rohs certified? - incompatible incompatible - incompatible - incompatible
Manufacturer packaging code - UK UK - UK - UK
ECCN code - 3A991.C.3 3A991.C.3 - 3A991.C.3 - 3A991.C.3
JESD-609 code - e0 e0 - e0 - e0
Humidity sensitivity level - 1 1 - 1 - 1
Encapsulate equivalent code - LCC48,.27SQ,20 LCC48,.27SQ,20 - LCC48,.27SQ,20 - LCC48,.27SQ,20
Peak Reflow Temperature (Celsius) - 235 235 - 235 - 235
power supply - 3.3 V 3.3 V - 3.3 V - 3.3 V
Terminal surface - Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb)
Maximum time at peak reflow temperature - 20 20 - 20 - 20
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