Programmable Clock Generator
5P49V5935
DATASHEET
Description
The 5P49V5935 is a programmable clock generator intended
for high-performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I
2
C
interface. This is IDT’s fifth generation of programmable clock
technology (VersaClock
®
5).
The 5P49V5935 by default uses an integrated 25MHz crystal
as input reference. It also has a redundant external clock
input. A glitchless manual switchover functions allows
selection of either one as mentioned above as input reference
during normal operation.
Two select pins allow up to 4 different configurations to be
programmed and accessible using processor GPIOs or
bootstrapping. The different selections may be used for
different operating modes (full function, partial function, partial
power-down), regional standards (US, Japan, Europe) or
system production margin testing.
The device may be configured to use one of two I
2
C
addresses to allow multiple devices to be used in a system.
Features
•
Generates up to four independent output frequencies
•
High-performance, low phase noise PLL, < 0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1GbE and 10GbE
•
Four fractional output dividers (FODs)
•
Independent spread spectrum capability on each output
pair
•
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
•
I
2
C serial programming interface
•
One reference LVCMOS output clock
•
Four universal output pairs:
– Each configurable as one differential output pair or two
LVCMOS outputs
I/O standards:
– Single-ended I/Os: 1.8V to 3.3V LVCMOS
– Differential I/Os: LVPECL, LVDS and HCSL
•
Pin Assignment
OUT0_SEL_I2CB
•
Input frequency ranges:
– LVDS, LVPECL, HCSL differential clock input (CLKIN,
CLKINB) – 1MHz to 350MHz
Output frequency ranges:
– LVCMOS clock outputs: 1MHz to 200MHz
– LVDS, LVPECL, HCSL differential clock outputs: 1MHz
to 350MHz
•
OUT1B
V
DDO
0
V
DDO
1
OUT1
V
DDD
CLKIN
CLKINB
NC
NC
V
DDA
CLKSEL
24 23 22 21 20 19
1
18
2
3
4
5
6
7
8
17
•
Individually selectable output voltage (1.8V, 2.5V, 3.3V) for
V
DDO
2
OUT2
OUT2B
V
DDO
3
OUT3
OUT3B
each output pair
EPAD
16
15
14
13
9 10 11 12
SEL1/SDA
SEL0/SCL
•
•
•
•
•
•
•
•
•
Redundant clock inputs with manual switchover
Programmable loop bandwidth
Programmable output to output skew
Programmable slew rate control
Individual output enable/disable
Power-down mode
1.8V, 2.5V or 3.3V core V
DDD
, V
DDA
4 x 4 mm 24-LGA package
-40° to +85°C industrial temperature operation
SD/OE
V
DDO
4
OUT4
4 × 4 mm 24-LGA
5P49V5935 NOVEMBER 1, 2017
OUT4B
1
©2017 Integrated Device Technology, Inc.
5P49V5935 DATASHEET
Functional Block Diagram
V
DDO
0
OSC
25MHz
OUT0_SEL_I2CB
V
DDO
1
OUT1
FOD1
OUT1B
CLKIN
CLKINB
FOD2
OUT2B
CLKSEL
SD/OE
FOD3
SEL1/SDA
SEL0/SCL
OTP
and
Control Logic
V
DDO
2
OUT2
PLL
V
DDO
3
OUT3
OUT3B
V
DDO
4
OUT4
FOD4
OUT4B
V
DDA
V
DDD
Applications
•
•
•
•
•
•
•
•
•
•
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1GbE and 10GbE
PROGRAMMABLE CLOCK GENERATOR
2
NOVEMBER 1, 2017
5P49V5935 DATASHEET
Table 1: Pin Descriptions
Number
1
2
3
4
5
Name
CLKIN
CLKINB
NC
NC
VDDA
Input
Input
--
--
Power
Type
Pull-down
Pull-down
Description
Differential clock input. Weak 100kohms internal pull-down.
Complementary differential clock input. Weak 100kohms internal pull-down.
No connect.
No connect.
Analog functions power supply pin. Connect to 1.8V to 3.3V. VDDA and VDDD
should have the same voltage applied.
Input clock select. Selects the active input reference source, when in Manual
switchover mode.
0 = Integrated crystal (default)
1 = CLKIN, CLKINB
CLKSEL Polarity can be changed by I2C programming as shown in Table 4.
Enables/disables the outputs (OE) or powers down the chip (SD). The SH bit
controls the configuration of the SD/OE pin. The SH bit needs to be high for
SD/OE pin to be configured as SD. The SP bit (0x02) controls the polarity of the
signal to be either active HIGH or LOW only when pin is configured as OE
(Default is active LOW.) Weak internal pull down resistor. When configured as
SD, device is shut down, differential outputs are driven high/low, and the single-
ended LVCMOS outputs are driven low. When configured as OE, and outputs are
disabled, the outputs can be selected to be tri-stated or driven high/low,
depending on the programming bits as shown in the SD/OE Pin Function Truth
table.
Configuration select pin, or I2C SDA input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Configuration select pin, or I2C SCL input as selected by OUT0_SEL_I2CB.
Weak internal pull down resistor.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT4/OUT4B.
Output Clock 4. Please refer to the Output Drivers section for more details.
Complementary Output Clock 4. Please refer to the Output Drivers section for
more details.
Complementary Output Clock 3. Please refer to the Output Drivers section for
more details.
Output Clock 3. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT3/OUT3B.
Complementary Output Clock 2. Please refer to the Output Drivers section for
more details.
Output Clock 2. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT2/OUT2B.
Complementary Output Clock 1. Please refer to the Output Drivers section for
more details.
Output Clock 1. Please refer to the Output Drivers section for more details.
Output power supply. Connect to 1.8 to 3.3V. Sets output voltage levels for
OUT1/OUT1B.
Digital functions power supply pin. Connect to 1.8 to 3.3V. VDDA and VDDB
should have the same voltage applied.
Power supply pin for OUT0_SEL_I2CB. Connect to 1.8 to 3.3V. Sets output
voltage levels for OUT0.
Latched input/LVCMOS Output. At power up, the voltage at the pin
OUT0_SEL_I2CB is latched by the part and used to select the state of pins 8
and 9. If a weak pull up (10Kohms) is placed on OUT0_SEL_I2CB, pins 8 and 9
will be configured as hardware select pins, SEL1 and SEL0. If a weak pull down
(10Kohms) is placed on OUT0_SEL_I2CB or it is left floating, pins 8 and 9 will
act as the SDA and SCL pins of an I2C interface. After power up, the pin acts as
a LVCMOS reference output which is the same frequency as the input reference.
At default, 25MHz integrated crystal is used so OUT0 will also be 25MHz.
Connect to ground pad.
6
CLKSEL
Input
Pull-down
7
SD/OE
Input
Pull-down
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
SEL1/SDA
SEL0/SCL
VDDO4
OUT4
OUT4B
OUT3B
OUT3
VDDO3
OUT2B
OUT2
VDDO2
OUT1B
OUT1
VDDO1
VDDD
VDDO0
Input
Input
Power
Output
Output
Output
Output
Power
Output
Output
Power
Output
Output
Power
Power
Power
Pull-down
Pull-down
24
OUT0_SELB_I2C Input/Output
Pull-down
EPAD
VEE
Power
NOVEMBER 1, 2017
3
PROGRAMMABLE CLOCK GENERATOR
5P49V5935 DATASHEET
PLL Features and Descriptions
Spread Spectrum
To help reduce electromagnetic interference (EMI), the
5P49V5935 supports spread spectrum modulation. The
output clock frequencies can be modulated to spread energy
across a broader range of frequencies, lowering system EMI.
The 5P49V5935 implements spread spectrum using the
Fractional-N output divide, to achieve controllable modulation
rate and spreading magnitude. The Spread spectrum can be
applied to any output clock, any clock frequency, and any
spread amount from ±0.25% to ±2.5% center spread and
-0.5% to -5% down spread.
If OUT0_SEL_I2CB was 0 at POR, alternate configurations
can only be loaded via the I2C interface.
Table 4: Input Clock Select
Input clock select. Selects the active input reference source in
manual switchover mode.
0 = Integrated XTAL (default)
1 = CLKIN, CLKINB
CLKSEL polarity can be changed by I
2
C programming as
shown in the table below.
PRIMSRC
0
0
1
1
CLKSEL
0
1
0
1
Source
Integrated XTAL
CLKIN, CLKINB
CLKIN, CLKINB
Integrated XTAL
Table 2: Loop Filter
PLL loop bandwidth range depends on the input reference
frequency (Fref) and can be set between the loop bandwidth
range as shown in the table below.
Input Reference
Loop
Loop
Frequency–Fref Bandwidth Min Bandwidth Max
(MHz)
(kHz)
(kHz)
1
350
40
300
126
1000
PRIMSRC is bit 1 of Register 0x13.
Reference Clock Input Pins and
Selection
The 5P49V5935 by default uses an integrated 25MHz crystal
as input reference. It also has a redundant external clock
input. A glitchless manual switchover functions allows
selection of either one as mentioned above as input reference
during normal operation.
Either clock input can be set as the primary clock. The primary
clock designation is to establish which is the main reference
clock to the PLL. The non-primary clock is designated as the
secondary clock in case the primary clock goes absent and a
backup is needed. The PRIMSRC bit determines which clock
input will be selected as primary clock. When PRIMSRC bit is
“0”, integrated crystal is selected as the primary clock, and
when “1”, (CLKIN, CLKINB) as the primary clock.
The two reference inputs can be manually selected using the
CLKSEL pin. The SM bits must be set to “0x” for manual
switchover which is detailed in Manual Switchover Mode
section.
Table 3: Configuration Table
This table shows the SEL1, SEL0 settings to select the
configuration stored in OTP. Four configurations can be stored
in OTP. These can be factory programmed or user
programmed.
REG0:7 Config
OUT0_SEL_I2CB SEL1 SEL0
I
2
C
Access
at POR
1
1
1
1
0
0
0
0
1
1
X
X
0
1
0
1
X
X
No
No
No
No
Yes
Yes
0
0
0
0
1
0
0
1
2
3
I
2
C
defaults
0
At power up time, the SEL0 and SEL1 pins must be tied to
either the VDDD/VDDA power supply so that they ramp with
that supply or are tied low (this is the same as floating the
pins). This will cause the register configuration to be loaded
that is selected according to Table 3 above. Providing that
OUT0_SEL_I2CB was 1 at POR and OTP register 0:7 = 0,
after the first 10ms of operation the levels of the SELx pins can
be changed, either to low or to the same level as
VDDD/VDDA. The SELx pins must be driven with a digital
signal of < 300ns Rise/Fall time and only a single pin can be
changed at a time. After a pin level change, the device must
not be interrupted for at least 1ms so that the new values have
time to load and take effect.
PROGRAMMABLE CLOCK GENERATOR
4
Manual Switchover Mode
When SM[1:0] is “0x”, the redundant inputs are in manual
switchover mode. In this mode, CLKSEL pin is used to switch
between the primary and secondary clock sources. The
primary and secondary clock source setting is determined by
the PRIMSRC bit. During the switchover, no glitches will occur
at the output of the device, although there may be frequency
and phase drift, depending on the exact phase and frequency
relationship between the primary and secondary clocks.
NOVEMBER 1, 2017
5P49V5935 DATASHEET
OTP Interface
The 5P49V5935 can also store its configuration in an internal
OTP. The contents of the device's internal programming
registers can be saved to the OTP by setting burn_start
(W114[3]) to high and can be loaded back to the internal
programming registers by setting usr_rd_start(W114[0]) to
high.
To initiate a save or restore using I
2
C, only two bytes are
transferred. The Device Address is issued with the read/write
bit set to “0”, followed by the appropriate command code. The
save or restore instruction executes after the STOP condition
is issued by the Master, during which time the 5P49V5935 will
not generate Acknowledge bits. The 5P49V5935 will
acknowledge the instructions after it has completed execution
of them. During that time, the I
2
C bus should be interpreted as
busy by all other users of the bus.
On power-up of the 5P49V5935, an automatic restore is
performed to load the OTP contents into the internal
programming registers. The 5P49V5935 will be ready to
accept a programming instruction once it acknowledges its
7-bit I
2
C address.
Availability of Primary and Secondary I
2
C addresses to allow
programming for multiple devices in a system. The I
2
C slave
address can be changed from the default 0xD4 to 0xD0 by
programming the I2C_ADDR bit D0.
VersaClock 5
Programming Guide
provides detailed I
2
C programming
guidelines and register map.
Table 5: SD/OE Pin Function Truth Table
SH bit SP bit OSn bit OEn bit SD/OE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
x
0
1
1
1
0
1
1
1
0
1
1
0
1
1
x
x
0
1
1
x
0
1
1
x
0
1
x
0
1
x
x
x
0
1
x
x
0
1
0
0
0
0
0
0
1
2
OUTn
Tri-state
Output active
Output active
Output driven High Low
Tri-state
2
Output active
Output driven High Low
Output active
Tri-state
2
Output active
Output active
Tri-state
2
Output active
Output driven High Low
Output driven High Low
1
Note 1 : Global Shutdown
Note 2 : Tri-state regardless of OEn bits
Output Alignment
Each output divider block has a synchronizing POR pulse to
provide startup alignment between outputs. This allows
alignment of outputs for low skew performance. The phase
alignment works both for integer output divider values and for
fractional output divider values.
Besides the POR at power up, the same synchronization reset
is also triggered when switching between configurations with
the SEL0/1 pins. This ensures that the outputs remain aligned
in every configuration. This reset causes the outputs to
suspend for a few hundred microseconds so the switchover is
not glitch-less. The reset can be disabled for applications
where glitch-less switch over is required and alignment is not
critical.
When using I
2
C to reprogram an output divider during
operation, alignment can be lost. Alignment can be restored
by manually triggering the reset through I
2
C.
When alignment is required for outputs with different
frequencies, the outputs are actually aligned on the falling
edges of each output by default. Rising edge alignment can
also be achieved by utilizing the programmable skew feature
to delay the faster clock by 180 degrees. The programmable
skew feature also allows for fine tuning of the alignment.
For details of register programming, please see
VersaClock 5
Family Register Descriptions and Programming Guide
for
details.
SD/OE Pin Function
The polarity of the SD/OE signal pin can be programmed to be
either active HIGH or LOW with the SP bit (W16[1]). When SP
is “0” (default), the pin becomes active LOW and when SP is
“1”, the pin becomes active HIGH. The SD/OE pin can be
configured as either to shutdown the PLL or to enable/disable
the outputs. The SH bit controls the configuration of the
SD/OE pin The SH bit needs to be high for SD/OE pin to be
configured as SD
.
SP
SD/OE Input
OEn
SH
Global Shutdown
OSn
OUTn
When configured as SD, device is shut down, differential
outputs are driven High/low, and the single-ended LVCMOS
outputs are driven low. When configured as OE, and outputs
are disabled, the outputs are driven high/low.
NOVEMBER 1, 2017
5
PROGRAMMABLE CLOCK GENERATOR
京公网安备 11010802033920号
EEWORLD
