IS61LF6436A
IS61LF6432A
®
Long-term Support
World Class Quality
64Kx32, 64Kx36
SYNCHRONOUS FLOW-THROUGH STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Interleaved or linear burst sequence control us-
ing MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 100-Pin TQFP package
• Power Supply:
+3.3V V
dd
+3.3V or 2.5V V
ddq
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
• Industrial Temperature Available:
(-40
o
C to +85
o
C)
• Lead-free available
MAY 2017
DESCRIPTION
The
ISSI
IS61LF6432A and IS61LF6436A are high-speed,
low-power synchronous static RAM designed to provide
a burstable, high-performance, memory. IS61LF6432A is
organized as 65,536 words by 32 bits. IS61LF6436A is
organized as 65,536 words by 36 bits. They are fabricated
with
ISSI
's advanced CMOS technology. The device inte-
grates a 2-bit burst counter, high-speed SRAM core, and
high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be writ-
ten. BWa controls DQa, BWb controls DQb, BWc controls
DQc, BWd controls DQd, conditioned by BWE being LOW.
A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally by the IS61LF6432A/36A and controlled by the
ADV (burst address advance) input pin.
The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW. Interleave
burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol
t
kq
t
kc
Parameter
Clock Access Time
Cycle Time
Frequency
8.5
8.5
11
90
Unit
ns
ns
MHz
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be ex-
pected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon
Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc. — www.issi.com
Rev. B1
05/08/2017
1
IS61LF6436A
IS61LF6432A
PIN CONFIGURATION
100-Pin TQFP
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
Vss
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
®
Long-term Support
World Class Quality
NC
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
NC
VDD
NC
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
NC
64K x 32
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address Sta-
tus
Synchronous Controller Address Sta-
tus
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE, CE2, CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
V
dd
+3.3V Power Supply
Vss
Ground
V
ddq
Isolated Output Buffer Supply: +3.3V
or 2.5V
ZZ
Snooze Enable
A
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B1
05/08/2017
MODE
A
A
A
A
A1
A0
NC
NC
Vss
VDD
NC
NC
A
A
A
A
A
A
NC
3
IS61LF6436A
IS61LF6432A
PIN CONFIGURATION
100-Pin TQFP
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VDD
Vss
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
®
Long-term Support
World Class Quality
DQPc
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
NC
VDD
NC
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
DQPb
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
64K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
Synchronous Address Inputs
Synchronous Clock
Synchronous Processor Address
Status
Synchronous Controller Address
Status
Synchronous Burst Address Advance
Individual Byte Write Enable
Synchronous Byte Write Enable
GW
Synchronous Global Write Enable
CE, CE2, CE2
Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
MODE Burst Sequence Mode Selection
V
dd
+3.3V Power Supply
Vss
Ground
V
ddq
Isolated Output Buffer Supply: +3.3V or
2.5V
ZZ
Snooze Enable
DQPa-DQPd Parity Data I/O
A
CLK
ADSP
ADSC
ADV
BWa-BWd
BWE
MODE
A
A
A
A
A1
A0
NC
NC
Vss
VDD
NC
NC
A
A
A
A
A
A
NC
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B1
05/08/2017
IS61LF6436A
IS61LF6432A
TRUTH TABLE
Operation
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Deselected, Power-down
Read Cycle, Begin Burst
Read Cycle, Begin Burst
Write Cycle, Begin Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Read Cycle, Continue Burst
Write Cycle, Continue Burst
Write Cycle, Continue Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Read Cycle, Suspend Burst
Write Cycle, Suspend Burst
Write Cycle, Suspend Burst
Address
Used
CE
None
H
None
L
None
L
None
X
None
X
External L
External L
External L
Next
X
Next
X
Next
H
Next
H
Next
X
Next
H
Current X
Current X
Current H
Current H
Current X
Current H
CE2
X
X
L
X
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
CE2
X
H
X
H
X
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
ADSP ADSC
X
L
L
X
L
X
H
L
H
L
L
X
H
L
H
L
H
H
H
H
X
H
X
H
H
H
X
H
H
H
H
H
X
H
X
H
H
H
X
H
ADV
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
®
Long-term Support
World Class Quality
WRITE
X
X
X
X
X
X
Read
Write
Read
Read
Read
Read
Write
Write
Read
Read
Read
Read
Write
Write
OE
X
X
X
X
X
X
X
X
L
H
L
H
X
X
L
H
L
H
X
X
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
Q
Q
D
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
PARTIAL TRUTH TABLE
Function
Read
Read
Write Byte 1
Write All Bytes
Write All Bytes
GW
H
H
H
H
L
BWE
H
L
L
L
X
BWa
X
H
L
L
X
BWb
X
H
H
L
X
BWc
X
H
H
L
X
BWd
X
H
H
L
X
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. B1
05/08/2017
5
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