STD11NM65N, STF11NM65N,
STFI11NM65N, STP11NM65N
N-channel 650 V, 0.425
Ω
typ., 11 A MDmesh™II Power MOSFET
in DPAK, TO-220FP, I²PAKFP and TO-220 packages
Datasheet
-
production data
TAB
Features
3
1
Order codes
3
2
1
V
DSS
@
T
Jmax
R
DS(on)
max
I
D
DPAK
STD11NM65N
STF11NM65N
710 V
STFI11NM65N
STP11NM65N
< 0.455
Ω
11 A
TO-220FP
TAB
1
3
2
3
•
100% avalanche tested
•
Low input capacitance and gate charge
•
low gate input resistance
1
2
I²PAKFP
TO-220
Figure 1. Internal schematic diagram
Applications
•
Switching applications
Description
These devices are N-channel Power MOSFETs
developed using the second generation of
MDmesh™ technology. This revolutionary Power
MOSFET associates a vertical structure to the
company’s strip layout to yield one of the world’s
lowest on-resistance and gate charge. It is
therefore suitable for the most demanding high
efficiency converters.
Table 1. Device summary
Order codes
STD11NM65N
STF11NM65N
11NM65N
STFI11NM65N
STP11NM65N
I²PAKFP
TO-220
Tube
Marking
Packages
DPAK
TO-220FP
Packaging
Tape and reel
July 2013
This is information on a product in full production.
Doc ID 13476 Rev 4
1/21
www.st.com
Contents
STD11NM65N, STF11NM65N, STFI11NM65N, STP11NM65N
Contents
1
2
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
.......................... 6
3
4
5
6
Test circuits
.............................................. 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2/21
Doc ID 13476 Rev 4
STD11NM65N, STF11NM65N, STFI11NM65N, STP11NM65N
Electrical ratings
1
Electrical ratings
Table 2. Absolute maximum ratings
Value
Symbol
Parameter
TO-220, DPAK
V
DS
V
GS
I
D
I
D
I
DM (2)
P
TOT
I
AR
Drain-source voltage
Gate-source voltage
Drain current (continuous) at T
C
= 25 °C
Drain current (continuous) at T
C
= 100 °C
Drain current (pulsed)
Total dissipation at T
C
= 25 °C
Avalanche current, repetitive or not-repetitive
(pulse width limited by T
j
max)
Single pulse avalanche energy
(starting T
j
= 25 °C, I
D
= I
AR
, V
DD
= 50 V)
Peak diode recovery voltage slope
Insulation withstand voltage (RMS) from all three
leads to external heat sink
(t = 1 s; T
C
= 25 °C)
Storage temperature
Max. operating junction temperature
- 55 to 150
150
11
7
44
110
3
650
± 25
11
(1)
7
(1)
44
(1)
25
TO-220FP
I²PAKFP
Unit
V
V
A
A
A
W
A
E
AS
dv/dt
(3)
147
15
mJ
V/ns
V
ISO
2500
V
T
stg
T
j
°C
°C
1. Limited by maximum junction temperature.
2. Pulse width limited by safe operating area.
3. I
SD
≤
11 A, di/dt
≤
400 A/μs; V
Peak
< V
(BR)DSS,
V
DD
≤
80% V
(BR)DSS
Table 3. Thermal data
Value
Symbol
Parameter
DPAK TO-220FP I²PAKFP TO-220
R
thj-case
R
thj-amb
Thermal resistance junction-case max
Thermal resistance junction-ambient
max
50
1.14
5
62.5
1.14
°C/W
°C/W
°C/W
Unit
R
thj-pcb (1)
Thermal resistance junction-pcb max
1. When mounted on 1inch² FR-4 board, 2 oz Cu
Doc ID 13476 Rev 4
3/21
21
Electrical characteristics
STD11NM65N, STF11NM65N, STFI11NM65N, STP11NM65N
2
Electrical characteristics
(T
C
= 25 °C unless otherwise specified)
Table 4. On /off states
Symbol
V
(BR)DSS
Parameter
Drain-source
breakdown voltage
Test conditions
I
D
= 1 mA, V
GS
= 0
Min.
650
1
100
± 100
2
3
0.425
4
0.455
Typ.
Max.
Unit
V
μA
μA
nA
V
Ω
I
DSS
Zero gate voltage
V
DS
= 650 V
drain current (V
GS
= 0) V
DS
= 650 V, T
C
=125 °C
Gate-body leakage
current (V
DS
= 0)
V
GS
= ± 25 V
I
GSS
V
GS(th)
R
DS(on)
Gate threshold voltage V
DS
= V
GS
, I
D
= 250
μA
Static drain-source on-
V
GS
= 10 V, I
D
= 5.5 A
resistance
Table 5. Dynamic
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
pF
pF
pF
pF
pF
C
iss
Input capacitance
V
DS
= 50 V, f = 1 MHz,
V
GS
= 0
-
800
-
C
oss
C
rss
C
oss eq.(1)
R
G
Q
g
Q
gs
Q
gd
Output capacitance
Reverse transfer
capacitance
Equivalent output
capacitance
Intrinsic gate
resistance
Total gate charge
Gate-source charge
Gate-drain charge
-
-
50
2.9
-
-
V
DS
= 0 to 520 V, V
GS
= 0
f = 1 MHz open drain
V
DD
= 520 V, I
D
= 11 A,
V
GS
= 10 V
(see
Figure 19)
-
133
-
pF
Ω
nC
nC
nC
-
-
-
-
4.2
29
3.9
16
-
-
-
-
1. C
oss eq.
is defined as a constant equivalent capacitance giving the same charging time as C
oss
when V
DS
increases from 0 to 80% V
DSS
4/21
Doc ID 13476 Rev 4
STD11NM65N, STF11NM65N, STFI11NM65N, STP11NM65N
Electrical characteristics
Table 6. Switching times
Symbol
t
d (on)
t
r
t
d(off)
t
f
Parameter
Turn-on delay time
Rise time
Turn-off delay time
Fall time
V
DD
= 325 V, I
D
= 5.5 A,
R
G
= 4.7
Ω,
V
GS
= 10 V
(see
Figure 20
and
Figure 23)
Test conditions
Min.
-
-
-
-
Typ.
15.5
10.8
11
47
Max. Unit
-
-
-
-
ns
ns
ns
ns
Table 7. Source drain diode
Symbol
I
SD
I
SDM
(1)
Parameter
Source-drain current
Source-drain current (pulsed)
Forward on voltage
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Reverse recovery time
Reverse recovery charge
Reverse recovery current
Test conditions
Min.
-
Typ.
Max. Unit
11
44
1.6
A
A
V
ns
μC
A
ns
μC
A
V
SD (2)
t
rr
Q
rr
I
RRM
t
rr
Q
rr
I
RRM
I
SD
= 11 A, V
GS
= 0
I
SD
= 11 A, di/dt = 100 A/μs
V
DD
= 60 V (see
Figure 23)
-
-
-
-
418
4.4
21
530
5.6
21
I
SD
= 11 A, di/dt = 100 A/μs
V
DD
= 60 V, T
j
= 150 °C
(see
Figure 23)
-
-
-
1. Pulse width limited by safe operating area
2. Pulsed: pulse duration = 300
μs,
duty cycle 1.5%
Doc ID 13476 Rev 4
5/21
21
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