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ATSAMA5D28A-CUR

Description
Microprocessors - MPU Entry level SAMA5 - BGA GREEN, IND TEMP,MRLA,T&R
Categorysemiconductor    The embedded processor and controller   
File Size9MB,2615 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Environmental Compliance
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Microprocessors - MPU Entry level SAMA5 - BGA GREEN, IND TEMP,MRLA,T&R

ATSAMA5D28A-CUR Parametric

Parameter NameAttribute value
Product AttributeAttribute Value
ManufacturerMicrochip
Product CategoryMicroprocessors - MPU
RoHSDetails
Mounting StyleSMD/SMT
Package / CaseLFBGA-289
CoreARM Cortex A5
Number of Cores1 Core
Data Bus Width32 bit
Maximum Clock Frequency500 MHz
L1 Cache Instruction Memory32 kB
L1 Cache Data Memory32 kB
Operating Supply Voltage1.2 V
Minimum Operating Temperature- 40 C
Maximum Operating Temperature+ 85 C
Memory TypeL1/L2 Cache, ROM, SRAM
Data RAM Size128 kB
Data ROM Size160 kB
Interface Type2-Wire, Ethernet, CAN, I2C, SPI, UART, USB
Number of I/Os128 I/O
I/O Voltage1.65 V to 3.6 V
Instruction TypeFloating Point
L2 Cache Instruction / Data Memory128 kB
Number of Timers/Counters6 x 32 bit
Processor SeriesSAMA5D2
Factory Pack Quantity119
Watchdog TimersWatchdog Timer
32-BIT ARM-BASED
MICROPROCESSORS
SAMA5D2 Series
SAMA5D21 /22 /23 /24 /26 /27 /28
Introduction
The SAMA5D2 series is a high-performance, ultra-low-power ARM
®
Cortex
®
-A5 processor-based MPU running up to
500 MHz, with support for multiple memories such as DDR2, DDR3, DDR3L, LPDDR1, LPDDR2, LPDDR3, and QSPI
Flash. The devices integrate powerful peripherals for connectivity and user interface applications, and offer advanced
security functions (ARM TrustZone
®
, tamper detection, secure data storage, etc.), as well as high-performance crypto-
processors AES, SHA and TRNG.
The SAMA5D2 series is delivered with a free Linux distribution and bare metal C examples.
Features
• ARM Cortex-A5 core
- ARMv7-A architecture
- ARM TrustZone
- NEON
Media Processing Engine
- Up to 500 MHz
- ETM/ETB 8 Kbytes
• Memory Architecture
- Memory Management Unit
- 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
- 128-Kbyte L2 cache configurable to be used as an internal SRAM
- One 128-Kbyte scrambled internal SRAM
- One 160-Kbyte internal ROM
64-Kbyte scrambled and maskable ROM embedding boot loader/ Secure boot loader
96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
- High-bandwidth scramblable 16-bit or 32-bit Double Data Rate (DDR) multiport dynamic RAM controller sup-
porting up to 512 Mbyte 8-bank DDR2/DDR3 (DLL off only) / DDR3L (DLL off only) / LPDDR1/LPDDR2/
LPDDR3, including “on-the-fly” encryption/decryption path
- 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)
• System running up to 166 MHz in typical conditions
- Reset controller, shutdown controller, periodic interval timer, independent watchdog timer and secure Real-Time
Clock (RTC) with clock calibration
- One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for USB high speed
- Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz)
- Internal low-power 12 MHz RC and 32 KHz typical RC
- Selectable 32.768-Hz low-power oscillator and 8 to 24 MHz oscillator
- 51 DMA Channels including two 16-channel 64-bit Central DMA Controllers
- 64-bit Advanced Interrupt Controller (AIC)
- 64-bit Secure Advanced Interrupt Controller (SAIC)
- Three programmable external clock signals
• Low-Power Modes
- Ultra Low-power mode with fast wakeup capability
- Low-power Backup mode with 5-Kbyte SRAM and SleepWalking
features
Wakeup from up to nine wakeup pins, UART reception, analog comparison
Fast wakeup capability
2017 Microchip Technology Inc.
DS60001476B-page 1
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