Changes to Shutdown Section and Figure 16 ............................. 12
Changes to Table 7.......................................................................... 14
Changes to Table 8.......................................................................... 15
Changes to Table 9.......................................................................... 16
Changes to Table 12, Table 13, and Table 14............................... 17
Changes to Ordering Guide .......................................................... 24
4/09—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
SPECIFICATIONS
T
A
= −55°C to +150°C; V
DD
= 2.7 V to 5.5 V; unless otherwise noted.
Table 1.
Parameter
TEMPERATURE SENSOR AND ADC
Accuracy
1
Min
Typ
−0.05
Max
±0.4
2
±0.44
±0.5
±0.5
±0.7
±0.8
±1.0
Unit
°C
°C
°C
°C
°C
°C
°C
Bits
Bits
Test Conditions/Comments
ADT7310
ADC Resolution
13
16
T
A
= −40°C to +105°C, V
DD
= 3.0 V
T
A
= −40°C to +105°C, V
DD
= 2.7 V to 3.3 V
T
A
= −55°C to +125°C, V
DD
= 3.0 V
T
A
= −40°C to +105°C, V
DD
= 2.7 V to 3.6 V
T
A
= −55°C to +150°C, V
DD
= 2.7 V to 3.6 V
T
A
= −40°C to +105°C, V
DD
= 4.5 V to 5.5 V
T
A
= −55°C to +150°C, V
DD
= 2.7 V to 5.5 V
Twos complement temperature value of sign bit plus 12 ADC bits
(power-up default resolution)
Twos complement temperature value of sign bit plus 15 ADC bits
(Bit 7 = 1 in the configuration register)
13-bit resolution (sign + 12-bit)
16-bit resolution (sign + 15-bit)
Continuous conversion and one-shot conversion mode
First conversion on power-up only
Conversion time for 1 SPS mode
Temperature cycle = 25°C to 125°C, and back to 25°C
T
A
= 25°C
T
A
= 25°C
CT and INT pins pulled up to 5.5 V
V
OH
= 5 .5V
I
OL
= 2 mA @ 5.5 V, I
OL
= 1 mA @ 3.3 V
Temperature Resolution
13-Bit
16-Bit
Temperature Conversion Time
Fast Temperature Conversion Time
1 SPS Conversion Time
Temperature Hysteresis
Repeatability
3
DC PSRR
DIGITAL OUTPUTS (OPEN DRAIN)
High Output Leakage Current, I
OH
Output High Current
Output Low Voltage, V
OL
Output High Voltage, V
OH
Output Capacitance, C
OUT
DIGITAL INPUTS
Input Current
Input Low Voltage, V
IL
Input High Voltage, V
IH
Pin Capacitance
DIGITAL OUTPUT (DOUT)
Output High Voltage, V
OH
Output Low Voltage, V
OL
Output Capacitance, C
OUT
POWER REQUIREMENTS
Supply Voltage
Supply Current
At 3.3 V
At 5.5 V
1 SPS Current
At 3.3V
At 5.5V
Shutdown Current
At 3.3 V
At 5.5 V
Power Dissipation Normal Mode
Power Dissipation 1 SPS
1
2
0.0625
0.0078
240
6
60
±0.002
±0.015
0.1
0.1
5
1
0.4
°C
°C
ms
ms
ms
°C
°C
°C/V
µA
mA
V
V
pF
µA
V
V
pF
V
V
pF
V
µA
µA
µA
µA
15
25
µA
µA
µW
µW
0.7 × V
DD
3
±1
0.4
0.7 × V
DD
5
V
OH
− 0.3
0.4
50
2.7
210
250
46
65
2.0
5.2
700
150
5.5
250
300
10
V
IN
= 0 V to V
DD
I
SOURCE
= I
SINK
= 200 µA
I
OL
= 200 µA
Peak current while converting, SPI interface inactive
Peak current while converting, SPI interface inactive
V
DD
= 3.3 V, 1 SPS mode, T
A
= 25°C
V
DD
= 5.5 V, 1 SPS mode, T
A
= 25°C
Supply current in shutdown mode
Supply current in shutdown mode
V
DD
= 3.3 V, normal mode at 25°C
Power dissipated for V
DD
= 3.3 V, T
A
= 25°C
Accuracy includes lifetime drift.
The equivalent 3 σ limits are ±0.33°C. This 3 σ specification is provided to enable comparison with other vendors who use these limits.
3
Based on a floating average of 10 readings.
Rev. A | Page 3 of 24
ADT7310
SPI TIMING SPECIFICATIONS
Data Sheet
T
A
= −55°C to +150°C, V
DD
= 2.7 V to 5.5 V, unless otherwise noted. All input signals are specified with rise time (t
R
) = fall time (t
F
) = 5 ns
(10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
Table 2.
Parameter
1, 2
t
1
t
2
t
3
t
4
t
5
t
6
Limit at T
MIN
, T
MAX
(B Version)
0
100
100
30
25
0
60
80
10
80
0
0
60
80
10
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns min
ns min
ns max
ns max
ns min
Conditions/Comments
CS falling edge to SCLK active edge setup time
3
SCLK high pulse width
SCLK low pulse width
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
SCLK active edge to data valid delay
3
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
Bus relinquish time after CS inactive edge
CS rising edge to SCLK edge hold time
CS falling edge to DOUT active time
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
SCLK inactive edge to DOUT high
t
74
t
8
t
9
t
10
1
2
Sample tested during initial release to ensure compliance. All input signals are specified with t
R
= t
F
= 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
See Figure 2.
3
SCLK active edge is falling edge of SCLK.
4
This means that the times quoted in the timing characteristics are the true bus relinquish times of the part and, as such, are independent of external bus loading
capacitances.
CS
t
1
t
2
1
2
t
3
3
7
8
1
2
7
t
8
8
SCLK
t
4
DIN
t
5
MSB
LSB
DOUT
MSB
LSB
Figure 2. Detailed SPI Timing Diagram
I
SINK
(1.6mA WITH V
DD
= 5V,
100µA WITH V
DD
= 3V)
TO
OUTPUT
PIN
1.6V
10pF
ISOURCE
(200µA WITH V
DD
= 5V,
100µA WITH V
DD
= 3V)
07789-004
Figure 3. Load Circuit for Timing Characterization
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