ATF1502AE-4 datasheet, PDF - EEWORLD Datasheet

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ATF1502AE-4: Description2nd Generation EE Complex Programmable Logic Devices; File Size576KB，76 Pages; ManufacturerAtmel (Microchip)

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ATF1502AE-4 Overview

2nd Generation EE Complex Programmable Logic Devices

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Features

•

2nd Generation EE Complex Programmable Logic Devices

– 3.0V to 3.6V Operating Range with 5V Tolerant I/Os

– 32 - 512 Macrocells with Enhanced Features

– Pin-compatible with Industry-standard Devices

– Speeds to 4.5 ns Maximum Pin-to-pin Delay

– Registered Operation to 225 MHz

Enhanced Macrocells with Logic Doubling

™

Features

– Bury Either Register or COM while Using the Other for Output

– Dual Independent Feedback Allows Multiple Latch Functions per Macrocell

– 5 Product Terms per Macrocell, Expandable to 40 per Macrocell with Cascade

Logic, Plus 15 More with Foldback Logic

– D/T/Latch Configurable Flip-flops plus Transparent Latches

– Global and/or per Macrocell Register Control Signals

– Global and/or per Macrocell Output Enable

– Programmable Output Slew Rate per Macrocell

– Programmable Output Open Collector Option per Macrocell

– Fast Registered Input from Product Term

Enhanced Connectivity

– Single Level Switch Matrix for Maximum Routing Options

– Up to 40 Inputs per Logic Block

Advanced Power Management Features

– ITD (Input Transition Detection) Available Individually on Global Clocks, Inputs and

I/O for µA Level Standby Current on “L” versions

– Pin-controlled 1 mA Standby Mode

– Reduced-power Option per Macrocell

– Automatic Power Down of Unused Macrocells

– Programmable Pin-keeper Inputs and I/Os

Available in Commercial and Industrial Temperature Ranges

Available in All Popular Packages Including PLCC, PQFP, TQFP and BGA

EE Technology

– 100% Tested

– Completely Reprogrammable

– 10,000 Program/Erase Cycles

– 20 Year Data Retention

– 2000V ESD Protection

– 200 mA Latch-up Immunity

JTAG Boundary-scan Testing Port per IEEE 1149.1-1990 and 1149.1a-1993

– Pull-up Option on JTAG Pins TMS and TDI

IEEE 1532 Compatibility for Fast In-System Programmability (ISP) via JTAG

PCI-compliant

Security Fuse Feature

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ATF15xxAE

Family

Datasheet

ATF1502AE(L)

ATF1504AE(L)

ATF1508AE(L)

ATF1516AE(L)

ATF1532AE(L)

Preliminary

•

Rev. 2398E–12/01

ATF15xxAE Family

Functional

Description

The ATF15xxAE Family of 3.3 Volt supply, high-performance, high-density complex program-

mable logic devices (CPLDs) utilizes Atmel’s proven electrically-erasable technology. With up

to 512 macrocells, they easily integrate logic from several TTL, SSI, MSI, LSI and classic

PLDs. The ATF15xxAE Family’s enhanced macrocell architecture, switch matrices and routing

increase usable gate count for new designs and increase odds of successful pin-locked

design modifications while maintaining pin-compatibility with industry-standard CPLDs.

The ATF15xxAE Family devices have four dedicated input pins and depending on the type of

device and package, up to 208 bi-directional I/O pins. Each dedicated input pin can also serve

as a global control signal, register clock, register reset or output enable. Each of these control

signals can be selected for use individually within each macrocell. Each input and I/O pin also

feeds into the global bus.

The macrocells are organized into groups of sixteen called logic blocks. The switch matrix in

each logic block selects 40 individual signals from the global bus. Macrocells within a given

logic block may share their sixteen foldback signals on a regional foldback bus. Cascade logic

between macrocells in the Logic Block allows fast, efficient generation of complex logic func-

tions. All macrocells are capable of being I/Os; however, the actual number of I/O pins

depends on the device and package type. The ATF15xxAE Family members contain two, four,

eight, sixteen or thirty-two such logic blocks, each capable of creating sum term logic with a

fan-in of 40 inputs from the switch matrix having access to up to 80 product terms.

Unused macrocells are automatically disabled by the fitter software to decrease power con-

sumption. A security fuse, when programmed, protects the contents of the other fuses. Two

bytes (16 bits) of User Signature are accessible to the user for purposes such as storing

project name, part number, revision or date. The User Signature is accessible regardless of

the state of the security fuse.

The ATF15xxAE Family devices are In-System Programmable (ISP) devices. They use the

industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and are fully-compliant with

JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro-

grammed without removing it from the printed circuit board. In addition to simplifying the

manufacturing flow, ISP also allows design modifications to be made in the field via software.

Global Bus/Switch

Matrix

The global bus (Figure 1) contains all input and I/O pin signals as well as the buried feedback

signals from all macrocells. The switch matrix in each logic block receives as its inputs all sig-

nals from the global bus. Up to 40 of these signals can be selected as inputs to the individual

logic blocks by the fitter software. Atmel’s ATF15xx Family of CPLDs use a single level switch

matrix signal distribution structure, where each logic block input has access to the same num-

ber of global bus inputs, maximizing the number of possible ways to route a global bus signal.

This single level structure is in contrast with split switch matrix structures used by others in

which routing a particular global bus input to a particular logic block input makes that signal

unavailable to some other logic blocks, thus greatly limiting the available opportunities to

route.

The ATF15xxAE Family macrocell, shown in Figure 2, consists of five sections: product terms

and product term select multiplexer, OR/XOR/CASCADE logic, foldback bus, a flip-flop and

output buffer. Extra fan-in and signal routing are provided throughout. Each macrocell can

generate a foldback logic term from the product term mux and a buried feedback with extra

routing that go to the global bus.

2398E–12/01

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