EEWORLDEEWORLDEEWORLD

Part Number

Search

530UA1086M00DGR

Description
CMOS/TTL Output Clock Oscillator, 1086MHz Nom, ROHS COMPLIANT, SMD, 6 PIN
Categoryoscillator   
File Size215KB,12 Pages
ManufacturerSilicon Laboratories Inc
Environmental Compliance  
Download Datasheet Parametric View All

530UA1086M00DGR Overview

CMOS/TTL Output Clock Oscillator, 1086MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

530UA1086M00DGR Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerSilicon Laboratories Inc
package instructionROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Codeunknown
Is SamacsysN
Other featuresTAPE AND REEL
maximum descent time0.35 ns
Frequency Adjustment - MechanicalNO
frequency stability50%
JESD-609 codee4
Manufacturer's serial number530
Installation featuresSURFACE MOUNT
Nominal operating frequency1086 MHz
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Oscillator typeCMOS/TTL
physical size7.0mm x 5.0mm x 1.85mm
longest rise time0.35 ns
Maximum supply voltage2.75 V
Minimum supply voltage2.25 V
Nominal supply voltage2.5 V
surface mountYES
maximum symmetry55/45 %
Terminal surfaceNickel/Gold (Ni/Au)
Base Number Matches1
S i 5 3 0 / 5 31
R
EVISION
D
C
R Y S TA L
O
S C I L L A T O R
(XO)
(10 M H
Z T O
1.4 G H
Z
)
Features
Available with any-rate output
frequencies from 10 MHz to 945 MHz
and select frequencies to 1.4 GHz
3rd generation DSPLL
®
with superior
jitter performance
3x better frequency stability than
SAW-based oscillators
Internal fixed crystal frequency
ensures high reliability and low
aging
Available CMOS, LVPECL,
LVDS, and CML outputs
3.3, 2.5, and 1.8 V supply options
Industry-standard 5 x 7 mm
package and pinout
Pb-free/RoHS-compliant
Si5602
Ordering Information:
See page 7.
Applications
SONET/SDH
Networking
SD/HD video
Test and measurement
Clock and data recovery
FPGA/ASIC clock generation
Pin Assignments:
See page 6.
(Top View)
NC
OE
GND
1
2
3
6
5
4
V
DD
Description
The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry
to provide a low jitter clock at high frequencies. The Si530/531 is available
with any-rate output frequency from 10 to 945 MHz and select frequencies to
1400 MHz. Unlike a traditional XO, where a different crystal is required for
each output frequency, the Si530/531 uses one fixed crystal to provide a
wide range of output frequencies. This IC based approach allows the crystal
resonator to provide exceptional frequency stability and reliability. In addition,
DSPLL clock synthesis provides superior supply noise rejection, simplifying
the task of generating low jitter clocks in noisy environments typically found in
communication systems. The Si530/531 IC based XO is factory configurable
for a wide variety of user specifications including frequency, supply voltage,
output format, and temperature stability. Specific configurations are factory
programmed at time of shipment, thereby eliminating long lead times
associated with custom oscillators.
®
CLK–
CLK+
Si530 (LVDS/LVPECL/CML)
OE
NC
GND
1
2
3
6
5
4
V
DD
Functional Block Diagram
V
DD
CLK– CLK+
NC
CLK
Si530 (CMOS)
Fixed
Frequency
XO
Any-rate
10–1400 MHz
DSPLL
®
Clock
Synthesis
OE
NC
GND
1
2
3
6
5
4
V
DD
CLK–
CLK+
Si531 (LVDS/LVPECL/CML)
OE
GND
Rev. 1.1 6/07
Copyright © 2007 by Silicon Laboratories
Si530/531
Let's play with Raspberry Pi 3+. If you want to do your work well, you must first sharpen your tools.
[i=s]This post was last edited by shenlan1986 on 2016-11-4 21:47[/i] The Raspberry Pi has been installed. The normal boot is only the first step of a long journey. In order to improve the user experie...
shenlan1986 Embedded System
The internal resistance of the STM32RTC power supply pin to ground is 3K?
I found that the mass-produced products always lost the clock, and the result was that the battery was dead. Then I measured the resistance of the RTC power supply pin to ground in the off state, and ...
8306593 stm32/stm8
How does DSP2808 implement CAN bus to send data to the host computer?
Previously, I sent data to the host computer through USBCAN2I on dsp2812. Now I want to implement the corresponding function on 2808. I typed it on dsp2808 according to the function of the code on dsp...
hebolovecjj DSP and ARM Processors
More than 90 people from a research institute in Hefei, Chinese Academy of Sciences, resigned collectively. The personnel department said: They were poached
In response to media reports that more than 90 researchers from the Institute of Nuclear Energy Safety Technology of the Chinese Academy of Sciences (hereinafter referred to as the "Nuclear Safety Ins...
eric_wang Talking
【KW41z】Access the Thread network terminal from the public network to turn on the lights
[i=s]This post was last edited by ljj3166 on 2017-7-5 11:26[/i] Using the external network to access the Thread network is a very important part of the original poster's idea. The terminals of the Thr...
ljj3166 NXP MCU
74 series IP packaging based on FPGA vivado 2017.2
74 Series IP Packaging Experiment Guide Based on FPGA Vivado 2017.2 1. Experimental Purpose Master two ways to package IP: GUI and Tcl 2. Experimental Content This experimental guide takes 74LS00 IP p...
大辉哥0614 FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 2288  1539  2439  961  2107  47  31  50  20  43 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号