Audio Codec for Recordable DVD
ADAV801
FEATURES
Stereo analog-to-digital converter (ADC)
Supports 48 kHz/96 kHz sample rates
102 dB dynamic range
Single-ended input
Automatic level control
Stereo digital-to-analog converter (DAC)
Supports 32 kHz/44.1 kHz/48 kHz/96 kHz/192 kHz
sample rates
101 dB dynamic range
Single-ended output
Asynchronous operation of ADC and DAC
Stereo sample rate converter (SRC)
Input/output range: 8 kHz to 192 kHz
140 dB dynamic range
Digital interfaces
Record
Playback
Auxiliary record
Auxiliary playback
S/PDIF (IEC 60958) input and output
Digital interface receiver (DIR)
Digital interface transmitter (DIT)
PLL-based audio MCLK generators
Generates required DVDR system MCLKs
Device control via SPI-compatible serial port
64-lead LQFP package
XIN
FUNCTIONAL BLOCK DIAGRAM
SYSCLK1
SYSCLK2
SYSCLK3
CLATCH
MCLKO
MCLKI
COUT
XOUT
CCLK
CIN
PLL
CONTROL
REGISTERS
RECORD
DATA
OUTPUT
OLRCLK
OBCLK
OSDATA
OAUXLRCLK
OAUXBCLK
OAUXSDATA
DITOUT
VINL
VINR
VREF
ANALOG-TO-DIGITAL
CONVERTER
REFERENCE
SRC
DIGITAL
INPUT/OUTPUT
SWITCHING MATRIX
(DATAPATH)
AUX DATA
OUTPUT
VOUTL
VOUTR
DIGITAL-TO-ANALOG
CONVERTER
DIT
FILTD
PLAYBACK
DATA INPUT
AUX DATA
INPUT
DIR
ZEROL/INT
ZEROR
ADAV801
ISDATA
IAUXSDATA
ILRCLK
IBCLK
IAUXLRCLK
IAUXBCLK
DIRIN
Figure 1.
APPLICATIONS
DVD-recordable
All formats
CD-R/W
GENERAL DESCRIPTION
The ADAV801 is a stereo audio codec intended for applications
such as DVD or CD recorders that require high performance
and flexible, cost-effective playback and record functionality.
The ADAV801 features Analog Devices, Inc. proprietary, high
performance converter cores to provide record (ADC), playback
(DAC), and format conversion (SRC) on a single chip. The
ADAV801 record channel features variable input gain to allow
for adjustment of recorded input levels and automatic level
control, followed by a high performance stereo ADC whose
digital output is sent to the record interface. The record channel
also features level detectors that can be used in feedback loops
to adjust input levels for optimum recording. The playback
channel features a high performance stereo DAC with
independent digital volume control.
The sample rate converter (SRC) provides high performance
sample rate conversion to allow inputs and outputs that require
different sample rates to be matched. The SRC input can be
selected from playback, auxiliary, DIR, or ADC (record). The
SRC output can be applied to the playback DAC, both main and
auxiliary record channels, and a DIT.
Operation of the ADAV801 is controlled via an SPI-compatible
serial interface, which allows the programming of individual
control register settings. The ADAV801 operates from a single
analog 3.3 V power supply and a digital power supply of 3.3 V
with an optional digital interface range of 3.0 V to 3.6 V.
The part is housed in a 64-lead LQFP package and is character-
ized for operation over the commercial temperature range of
−40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved.
04577-001
ADAV801
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Test Conditions............................................................................. 3
ADAV801 Specifications ............................................................. 3
Timing Specifications .................................................................. 7
Temperature Range ...................................................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Functional Description .................................................................. 15
ADC Section ............................................................................... 15
DAC Section................................................................................ 18
Sample Rate Converter (SRC) Functional Overview ............ 19
PLL Section ................................................................................. 22
S/PDIF Transmitter and Receiver ............................................ 23
Serial Data Ports ......................................................................... 27
Interface Control ............................................................................ 30
SPI Interface ................................................................................ 30
Block Reads and Writes ............................................................. 30
Register Descriptions ..................................................................... 31
Layout Considerations................................................................... 58
ADC ............................................................................................. 58
DAC.............................................................................................. 58
PLL ............................................................................................... 58
Reset and Power-Down Considerations ................................. 58
Outline Dimensions ....................................................................... 59
Ordering Guide .......................................................................... 59
REVISION HISTORY
7/07—Rev. 0 to Rev. A
Changes to Table 1............................................................................ 3
Changes to ADC Section............................................................... 15
Changes to Figure 25...................................................................... 15
Changes to Figure 33...................................................................... 21
Changes to SRC Architecture Section ......................................... 21
Changes to Table 7.......................................................................... 22
Changes to Figure 36...................................................................... 22
Changes to Figure 39 and Figure 42............................................. 23
Changes to Transmitter Operation Section ................................ 27
Changes to Interrupts Section ...................................................... 27
Changes to Figure 50...................................................................... 28
Changes to Table 97........................................................................ 46
Changes to Table 101...................................................................... 47
Changes to Table 136 and Table 137 ............................................ 55
Updated Outline Dimensions ....................................................... 59
Changes to Ordering Guide .......................................................... 59
7/04—Revision 0: Initial Version
Rev. A | Page 2 of 60
ADAV801
SPECIFICATIONS
TEST CONDITIONS
Test conditions, unless otherwise noted.
Table 1.
Test Parameter
Supply Voltage
Analog
Digital
Ambient Temperature
Master Clock (MCLKI)
Measurement Bandwidth
Word Width (All Converters)
Load Capacitance on Digital Outputs
ADC Input Frequency
DAC Output Frequency
Digital Input
Digital Output
Condition
3.3 V
3.3 V
25°C
12.288 MHz
20 Hz to 20 kHz
24 bits
100 pF
1007.8125 Hz at −1 dBFS
960.9673 Hz at 0 dBFS
Slave mode, I
2
S justified format
Slave mode, I
2
S justified format
ADAV801 SPECIFICATIONS
Table 2.
Parameter
PGA SECTION
Input Impedance
Minimum Gain
Maximum Gain
Gain Step
REFERENCE SECTION
Absolute Voltage, V
REF
V
REF
Temperature Coefficient
ADC SECTION
Number of Channels
Resolution
Dynamic Range
Unweighted
A-Weighted
Total Harmonic Distortion + Noise
−88
−87
Analog Input
Input Range (± Full Scale)
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Offset
1.0
−1.5
−0.8
0.05
1
−10
dB
dB
V rms
dB
dB
mdB/°C
mV
Min
Typ
4
0
24
0.5
1.5
80
2
24
99
98
102
101
Max
Unit
kΩ
dB
dB
dB
V
ppm/°C
Comments
Bits
dB
dB
dB
dB
−60 dB input
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 48 kHz
f
S
= 96 kHz
Input = −1.0 dBFS
f
S
= 48 kHz
f
S
= 96 kHz
98
Rev. A | Page 3 of 60
ADAV801
Parameter
Crosstalk (EIAJ Method)
Volume Control Step Size (256 Steps)
Maximum Volume Attenuation
Mute Attenuation
Group Delay
f
S
= 48 kHz
f
S
= 96 kHz
ADC LOW-PASS DIGITAL DECIMATION FILTER
CHARACTERISTICS
1
Pass-Band Frequency
Stop-Band Frequency
Stop-Band Attenuation
Pass-Band Ripple
ADC HIGH-PASS DIGITAL FILTER CHARACTERISTICS
Cutoff Frequency
SRC SECTION
Resolution
Sample Rate
SRC MCLK
Maximum Sample Rate Ratios
Upsampling
Downsampling
Dynamic Range
Total Harmonic Distortion + Noise
DAC SECTION
Number of Channels
Resolution
Dynamic Range
Unweighted
A-Weighted
Total Harmonic Distortion + Noise
−91
−90
Analog Outputs
Output Range (± Full Scale)
Output Resistance
Common-Mode Output Voltage
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
DC Offset
1.0
60
1.5
−2
−0.8
0.05
1
+30
dB
dB
V rms
Ω
V
dB
dB
mdB/°C
mV
97
Min
Typ
−110
0.39
−48
∞
910
460
Max
Unit
dB
% per step
dB
dB
μs
μs
Comments
ADC outputs all zero codes
22
44
26
52
120
120
±0.01
±0.01
0.9
24
8
138 × f
S-
MAX
kHz
kHz
kHz
kHz
dB
dB
dB
dB
Hz
Bits
kHz
MHz
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 48 kHz
192
33
XIN = 27 MHz
f
S-MAX
is the greater of the input or
output sample rate
1:8
7.75:1
140
120
dB
20 Hz to f
S
/2, 1 kHz, −60 dBFS input,
f
IN
= 44.1 kHz, f
OUT
= 48 kHz
20 Hz to f
S
/2, 1 kHz, 0 dBFS input,
f
IN
= 44.1 kHz, f
OUT
= 48 kHz
2
24
99
98
101
100
Bits
dB
dB
dB
dB
20 Hz to 20 kHz, −60 dB input
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 48 kHz
f
S
= 96 kHz
Referenced to 1 V rms
f
S
= 48 kHz
f
S
= 96 kHz
−30
Rev. A | Page 4 of 60
ADAV801
Parameter
Crosstalk (EIAJ Method)
Phase Deviation
Mute Attenuation
Volume Control Step Size (256 Steps)
Group Delay
48 kHz
96 kHz
192 kHz
DAC LOW-PASS DIGITAL INTERPOLATION FILTER
CHARACTERISTICS
Pass-Band Frequency
Min
Typ
−110
0.05
−95.625
0.375
630
155
66
Max
Unit
dB
Degrees
dB
dB
μs
μs
μs
Comments
Stop-Band Frequency
Stop-Band Attenuation
Pass-Band Ripple
20
22
42
24
26
60
70
70
70
±0.002
±0.002
±0.005
27/54
27/54
256
256
256
512
768
768
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
dB
dB
dB
MHz
MHz
× f
S
× f
S
× f
S
f
S
= 44.1 kHz
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 44.1 kHz
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 44.1 kHz
f
S
= 48 kHz
f
S
= 96 kHz
f
S
= 44.1 kHz
f
S
= 48 kHz
f
S
= 96 kHz
PLL SECTION
Master Clock Input Frequency
Generated System Clocks
MCLKO
SYSCLK1
SYSCLK2
SYSCLK3
Jitter
SYSCLK1
SYSCLK2
SYSCLK3
DIR SECTION
Input Sample Frequency
Differential Input Voltage
DIT SECTION
Output Sample Frequency
DIGITAL I/O
Input Voltage High, V
IH
Input Voltage Low, V
IL
Input Leakage, I
IH
@ V
IH
= 3.3 V
Input Leakage, I
IL
@ V
IL
= 0 V
Output Voltage High, V
OH
@ I
OH
= 0.4 mA
Output Voltage Low, V
OL
@ I
OL
= −2 mA
Input Capacitance
256/384/512/768 × 32 kHz/
44.1 kHz/48 kHz
256/384/512/768 × 32 kHz/
44.1 kHz/48 kHz
256/512 × 32 kHz/44.1 kHz/
48 kHz
65
75
75
27.2
200
27.2
2.0
200
ps rms
ps rms
ps rms
kHz
mV
kHz
V
V
μA
μA
V
V
pF
200
DVDD
0.8
10
10
0.4
15
2.4
Rev. A | Page 5 of 60
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