Features ................................................................................................................................................................ 8
General Description ............................................................................................................................................ 10
Field Polynomial......................................................................................................................................... 11
Control Unit ................................................................................................................................................ 13
Puncturing Pattern File Format ........................................................................................................................... 14
Default Field Polynomials........................................................................................................................... 14
Signal Descriptions ............................................................................................................................................. 15
Block Size Type ......................................................................................................................................... 22
Memory Type ............................................................................................................................................. 22
Chapter 4. IP Core Generation............................................................................................................. 24
Licensing the IP Core.......................................................................................................................................... 24
Getting Started .................................................................................................................................................... 24
IPexpress-Created Files and Top Level Directory Structure............................................................................... 26
Instantiating the Core .......................................................................................................................................... 28
Enabling Hardware Evaluation in Diamond................................................................................................ 29
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 29
Updating/Regenerating the IP Core .................................................................................................................... 29
Regenerating an IP Core in Diamond ........................................................................................................ 29
Regenerating an IP Core in ispLEVER ...................................................................................................... 30
Chapter 5. Support Resources ............................................................................................................ 31
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
Telephone Support Hotline ........................................................................................................................ 31
E-mail Support ........................................................................................................................................... 31
Local Support ............................................................................................................................................. 31
Internet ....................................................................................................................................................... 31
Related Information............................................................................................................................................. 32
Revision History .................................................................................................................................................. 32
Appendix A. Resource Utilization ....................................................................................................... 33
LatticeECP and LatticeEC FPGAs ...................................................................................................................... 34
Ordering Part Number................................................................................................................................ 34
LatticeECP2 and LatticeECP2S FPGAs ............................................................................................................. 34
Ordering Part Number................................................................................................................................ 34
LatticeECP2M and LatticeECP2MS FPGAs ....................................................................................................... 35
Ordering Part Number................................................................................................................................ 35
Ordering Part Number................................................................................................................................ 35
Ordering Part Number................................................................................................................................ 36
Ordering Part Number................................................................................................................................ 36
LatticeSC and LatticeSCM FPGAs ..................................................................................................................... 37
Ordering Part Number................................................................................................................................ 37
IPUG52_01.6, December 2010
3
Dynamic Block Reed-Solomon Decoder User’s Guide
Chapter 1:
Introduction
Reed-Solomon codes are widely used in various communications and storage applications for forward error correc-
tion. Reed-Solomon codes are well suited for burst error correction and are frequently used as outer codes in com-
munication systems. A Reed-Solomon Decoder performs detection and correction of the encoded data at the
receiver. Lattice’s Dynamic Block Reed-Solomon Decoder (RS Decoder) IP core is compliant with several industry
standards including the more recent IEEE 802.16-2004 and can be custom configured to support other non-stan-
dard applications as well. The RS Decoder supports a wide range of symbol widths and allows the user to define
the field polynomial, generator polynomial and several other parameters.
The newer standards like IEEE 802.16-2004 require the use of Reed-Solomon codes with dynamically varying
block sizes. Lattice’s RS Decoder IP core provides an ideal solution that meets such needs of today’s forward error
correction world. This core allows the block size and number of check symbols to be varied dynamically through
input ports. Lattice’s RS Decoder IP can be used with Lattice’s RS Decoder for a complete Reed-Solomon code
based forward error correction application. For more information on these and other IP products for forward error
Could any kindhearted person send me a schematic diagram of the minimum FPGA system (FPGA chip is preferably Altera's cyclone series)... Urgent! Urgent! Please send it to my email address [email]69218...
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