For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
I
2
C is a registered trademark of Philips Semiconductors.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor-
mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade-
marks and service marks can be found at http://www.cirrus.com.
2
DS297DB3
CDB4340/41
1. CDB4340/41 SYSTEM OVERVIEW
The CDB4340/41 evaluation board is an excellent
means of quickly evaluating the CS4340/41. The
CS8414 digital audio interface receiver provides an
easy interface to digital audio signal sources in-
cluding the majority of digital audio test equip-
ment. The evaluation board also allows the user to
supply clocks and data through a 10-pin header for
system development.
The CDB4340/41 schematic has been partitioned
into 10 schematics shown in Figures 2 through 11.
Each partitioned schematic is represented in the
system diagram shown in Figure 1. Notice that the
the system diagram also includes the interconnec-
tions between the partitioned schematics.
formation mode. The information displayed by the
LED’s can be decoded by consulting the CS8414
data sheet. It is likely that the de-emphasis control
for the CS4340 will be erroneous and produce an
incorrect audio output if the Error Information
Switch is activated and the CS4340 is in the inter-
nal serial clock mode.
Encoded sample frequency information can be dis-
played provided a proper clock is being applied to
the FCK pin of the CS8414. When an LED is lit,
this indicates a "1" on the corresponding pin locat-
ed on the CS8414. When an LED is off, this indi-
cates a "0" on the corresponding pin. Neither the L
or R option of CSLR/FCK should be selected if the
FCK pin is being driven by a clock signal.
The evaluation board has been designed such that
the input can be either optical or coax (see
Figure 6). However, both inputs cannot be driven
simultaneously.
2. CS4340/41 DIGITAL TO ANALOG
CONVERTER
A description of the CS4340 is included in the
CS4340 data sheet. A description of the CS4341 is
included in the CS4341 data sheet.
4. CS8414 DATA FORMAT
The CS8414 data format can be set with jumpers
M0, M1, M2, and M3, as described the CS8414
datasheet. The format selected must be compatible
with the data format of the CS4340 or CS4341,
shown in the CS4340 and CS4341 datasheets.
Please note that the CS8414 does not support all the
possible modes of the CS4340 or CS4341, see Ta-
ble 1 for details. The default settings for M0-M3 on
the evaluation board are given in Tables 3-5.
CS4341 CS4340
CS8414
External Internal
Format Format
Format
SCLK
SCLK
0
-
2
Yes
Yes
1
0
2
Yes
No
2
1
0
No
Yes
3
2
Unsupported
-
-
4
-
Unsupported
-
-
5
3
5
Yes
No
6
-
6
Yes
Yes
7
0
2
Yes
No
Table 1. CS8414 Supported Formats
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard
S/PDIF data format using a CS8414 Digital Audio
Receiver, Figure 4. The outputs of the CS8414 in-
clude a serial bit clock, serial data, left-right clock
(FSYNC), de-emphasis control and a 256 Fs mas-
ter clock. The operation of the CS8414 and a dis-
cussion of the digital audio interface are included in
the CS8414 Datasheet.
During normal operation, the CS8414 operates in
the Channel Status mode where the LED’s display
channel status information for the channel selected
by the CSLR/FCK jumper. This allows the CS8414
to decode the de-emphasis bit from the digital au-
dio interface for control of the CS4340 de-empha-
sis filter.
When the Error Information Switch is activated,
the CS8414 operates in the Error and Frequency in-
DS297DB3
3
CDB4340/41
5. ANALOG OUTPUT FILTER
The evaluation board includes a pair of single pole
passive filters. The passive filters, Fig. 3, have a
corner frequency of approximately 95 kHz with
JP3 and JP6 installed and 190 kHz without JP3 and
JP6.
supply voltages, VCCA and VCCB, to the Voltage
Level Converter (LVXC4245) must remain within
2.25 Volts of each other in order to maintain proper
operation.
8. GROUNDING AND POWER SUPPLY
DECOUPLING
The CS4340/41 requires careful attention to power
supply and grounding arrangements to optimize
performance. Figure 10 details the power distribu-
tion used on this board. The CDB4340/41 ground
plane is split to control the digital return currents in
order to minimize digital interference. The decou-
pling capacitors are located as close to the
CS4340/41 as possible. Extensive use of ground
plane fill on both the analog and digital sections of
the evaluation board yields large reductions in radi-
ated noise.
6. INPUT/OUTPUT FOR CLOCKS AND
DATA
The evaluation board has been designed to allow
the interface to external systems via the 10-pin
header, J9. This header allows the evaluation board
to accept externally generated clocks and data. The
schematic for the clock/data I/O is shown in
Figure 11. The 74HC243 transceiver functions as
an I/O buffer where jumpers HDR1-HDR6 deter-
mine if the transceiver operates as a transmitter or
receiver. A transmit function is implemented with
the HDR1-HDR6 jumpers in the 8414 position.
LRCK, SDATA, and SCLK from the CS8414 will
be outputs on J9. The transceiver operates as a re-
ceiver with jumpers HDR1-HDR6 in the EXTER-
NAL position. MCLK, LRCK, SDATA and SCLK
on J9 become inputs.
9. CDB4341 CONTROL PORT
SOFTWARE
The CDB4341 is shipped with Windows based
software for interfacing with the CS4341 control
port via the DB25 connector, P1. The software can
be used to communicate with the CS4341 in either
SPI or I
2
C mode; however, in SPI mode the
CS4341 registers are write-only.
Run SETUP.EXE from the distribution diskette to
install the software. Further documentation for the
software is available on the distribution diskette.
The documentation is available in the plain text for-
mat file, README.TXT.
7. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by three
binding posts (GND, +5V, +3V/+5V) (see
Figure 10). The +5V input supplies power to the
+5 Volt digital circuitry (VA+5, VD+5, VDPC+5),
while the +3V/+5V input supplies power to the
Voltage Level Converter and the CS4340/41 for
evaluation in either +3 or +5 Volt mode. Note, the
4
DS297DB3
CDB4340/41
CONNECTOR
+5 V
+3V/+5V
GND
Digital input
Optical input
J9
Parallel Port
Control I/O
AOUTA
AOUTB
INPUT/OUTPUT
input
input
input
input
input
input/output
input/output
input/output
output
output
+ 5 Volt power
SIGNAL PRESENT
+ 3 Volt or + 5 Volt power for the CS4340/41 and the Voltage
Level Converter
ground connection from power supply
digital audio interface input via coax
digital audio interface input via optical
I/O for master, serial, left/right clocks and serial data
parallel connection to PC for SPI/I
2
C control port signals
I/O for SPI/I
2
C control port signals
channel A analog output with single-pole passive filter
channel B analog output with single-pole passive filter
京公网安备 11010802033920号
EEWORLD
